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HP 8753E - Page 24

HP 8753E
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4-2. Troubleshooting Organization
.................
4-9
4-3.
Al5
Prereguiator
LEDs
....................
4-10
44. kont Panel Power Up Sequence
...............
4-11
4-5. Equipment Setup for Source Power Check
...........
4-14
4-6.
ABUSNode
16: 1
V/GHz
................... 415
4-7. Equipment Setup
......................
4-16
4-8. Typical Measurement Trace
.................
4-17
4-9. HP 8753E
Overall
Block Diagram
...............
4-19
5-l.
Power Supply Group
SimpIified
Block Diagram
.........
5-3
5-2. Location of
Al5
Diagnostic
LEDs
...............
5-4
5-3.
A8
Post Regulator Test Point Locations
............
5-5
5-4. Removing the Line Fuse
...................
5-7
5-5. Power Supply Cable Locations
................
5-9
5-6.
A15Wl
Plug
Detail
......................
5-11
5-7.
kont
Panel Probe Power Connector Voltages
.........
5-20
5-8. Power Supply Block Diagram
.................
5-25
6-l.
Digital Control Group Block Diagram
.............
6-2
6-2. Switch Positions on the
A9
CPU
...............
6-5
6-3. CPU LED
Window
on Rear Panel
...............
6-6
6-4. Backlight Intensity Check Setup
...............
6-9
6-5. Newtons Rings.
.......................
6-11
6-6. Preset Sequence
.......................
6-13
7-l. Basic Phase Lock Error Troubleshooting Equipment Setup
... 74
7-2. Jumper Positions on the
A9
CPU
...............
7-5
7-3. Sampler/Mixer to Phase Lock Cable Connection Diagram
....
7-7
74. Waveform Integrity in SRC Tune Mode
............
7-9
7-5. Phase Locked Output Compared to Open Loop Output in SRC
Tune Mode.
.......................
7-9
7-6. 1
V/GHz
at Analog Bus Node 16 with Source PLL Off.
.....
7-11
7-7. YO- and YO+
Coil
Drive Voltage Differences with SOURCE
PLL
OFF
...........................
7-12
7-8. Sharp
109
kHz
pulses
at
A13TP5
(any frequency)
.......
7-16
7-9.HighBandREFSiiaI(~l6MHzCW).
............
7-17
7-10.
REF’SiiaIatAllTP9(5MHzCW)
..............
7-18
7-11. Typical
F’N
LO Waveform at
A12Jl
..............
7-19
7-12. 4 MHz Reference
SiiaI
at
A12TP9
(Preset)
..........
7-20
7-13. 90 Degree Phase Offset of High Band
2nd
LO
Siiais
(116
MHz
cw).
..........................
7-21
7-14. In-Phase Low Band 2nd LO
SiiaIs
(14 MHz
CW)
........
7-22
7-15. L
ENREP
Line at
A12P2-16
(Preset)
..............
7-23
7-16. Complementary L HB and L LB Signals (Preset)
........
7-24
Contents-19

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