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148 b EDN S
EPTEMBER 24, 1998
MCore uses a four-stage pipeline to execute two-thirds of its
95 basic instructions in one clock. Similar to Hitachi’s 32-bit
SuperH architecture, MCore uses 16-bit, fixed-length instruc-
tions and a register file with 16 general-purpose registers and
an alternative register file for context switches. Unlike
SuperH, which shadows only eight of its general-purpose reg-
isters, MCore shadows all 16. MCore implements only 86%
of its operation-code space, allowing some instruction head
room for future generations. The 16-bit instruction size forces
MCore to use two operand instructions—4 bits per register.
Motorola claims that the lack of three operand instructions
causes a 2 to 7% code bloat in key applications.
The architecture supports 8-, 16-, and 32-bit data types,
although misaligned data accesses for
ce a misaligned data
exception. You can mask the misaligned data exception using
a control bit in the process-status register. Although you can’t
access MCore’s registers as bytes and words, instructions can
sign-extend non-32-bit data types. A barrel shifter shifts as
many as 32 bits in one cycle. The architecture also contains
a find-first-one unit and result-feed-forward hardware. The
feed-forward hardware allows a subsequent operation to use
a result while the CPU writes the result back into the register
file. The first version of the MCore architecture offers limited
support for hardware multiply and divide; it uses a 2-bit per
clock, overlapped-scan, modified Booth algorithm with
early-out capability to reduce execution time for operations
with small multipliers.
MCore contains a 32-channel interrupt controller. The
processor can take in an asynchronous interrupt and get to
the first instruction of an interrupt-service routine in six
clocks. The CPU determines interrupt prioritization through
software, and you can use the find-first-one instruction to
scan for the highest priority interrupt and use the resulting
value as an offset into a jump table. An interrupt-control bit
in the program-status register allows an event to interrupt
multicycle instructions, such as the load/store multiple-reg-
ister instructions. For applications that are less real-time-crit-
ical, you can set this bit to prevent the interrupts from break-
ing into instructions.
MCore’s hardware-accelerator interface supports a variety
of application-specific functions. You can use one of several
interface mechanisms. For example, a register-snooping
mechanism reflects updates of MCore’s registers across the
interface without explicit passing of parameters from the core
to the hardware accelerator.
Power management: Besides a 16-bit external interface to
minimize power consumption, MCore also implements three
software-controlled low-power modes and controls func-
tional-unit clocking. The core runs as low as 1V, although the
first products operate from 1.8 to 3.3V.
Development tools: To support the development tools for
MCore, Motorola has established a validation center to ensure
that third-party vendors comply with the Motorola-defined
Application Binary Interface (ABI). ABI ensures that MCore
tools will work together in a development environment.
The 68EC000, a base for the 680x0 and 683xx lines of 32-bit
mPs, mixes 16- and 32-bit architectures. It has 32-bit registers
for easy addressing, a 16-bit datapath and ALU to conserve
silicon, and 16-bit instructions. Programmers get eight gen-
eral-purpose, 32-bit data registers, which the CPU can address
by bit, BCD, byte, word, or double word. In addition to user
and supervisor stack pointers, 68EC000 chips have seven
address registers. Other registers include the 32-bit program-
counter and 16-bit status registers. The status register main-
tains status for the user and supervisor modes with ser and
supervisor bytes. The 68EC000 implements user and super-
visor modes in hardware, which eases having a control ker-
nel or OS manage multiple application tasks.
The 68EC000 has microcode and second-level, expanded-
nanocode microcode levels. Instruction execution triggers a
chain of 10-bit microcode words. Each microcode word can
reference another word, such as a jump in microcode or a
string of 70-bit nanocode words that directly drive the CPU
logic.
The CPU lacks a memory controller, but the separate
address and data buses eliminate the need for buffering
addresses. However, the CPU needs logic to generate the
required DTACK* signal, which marks the successful com
-
pletion of a memor
y cycle. An address decoder is necessary
for multiple memory chips, and drivers may be necessar
y to
buffer bus address and data lines. (Integrated versions of the
68EC000 contain this logic.) If DT
ACK* is late, the CPU gen-
erates wait states.
Power management: Only the integrated versions provide
variations of sleep and low-power-stop modes.
Special instructions: The chip restricts privileged instruc-
tions—reset, stop, moves, and operations on the status regis
-
ter—to super
visor mode. To support user and super
visor
modes, the hardware implements separate stacks and pushes
and pops the program counter and status register onto the
stack for exceptions. A link instruction lets you build link lists
on private stacks. A special instruction lets you move as many
as 16 registers to or from an effective address, including
blocks of data registers to or from address registers.
Development tools: Green Hills Software (www
.ghs.com)
provides C, C++, Fortran, Pascal, and Ada compilers for the
68K ar
chitectures. This company also provides its Multi soft-
ware-development environment for developing programs
from these languages and mixing them into a single exe-
cutable program in almost any combination. Hewlett-
Packard (www.hp.com) offers logic analyzers, oscilloscopes,
emulators/analyzers, software simulators, debugger/emula-
tor software, a real-time software-performance analyzer, C
compilers, assemblers, linkers, and a debugging utility for
RTOSs. Huntsville Microsystems (www.hmi.com) supplies
emulators, a $199 background-mode debugger (BMD), and
simulators for Motorola devices. The company offers its HMI-
200 Series and SPS-2000 Series emulators. Integrated Systems
(www.isi.com), Microtec (www
.microtec.com), and Micro
-
ware (www
.microware.com) provide RTOSs and a variety of
other software tools to support hardware and software inte
-
gration. Intermetrics (www.intermetrics.com) offers compil
-
ers, assemblers, utilities, debuggers, and royalty-free real-time
kernels. Orion Instruments (www
.yokogawa.com) offers in-
circuit emulators and high-level-language sour
ce debuggers
for W
indows or Unix hosts. Software Development Systems
(www
.sdsi.com) provides C and C++ compilers; assemblers;
simulators; debuggers for the target monitor
, BDM, and JTAG;
and interactive development and debugging environments.
W
ind River Systems (www.windriver
.com) provides an RTOS,
networking facilities, and a set of cross-development tools.
W
ind River also provides a diagnostic and analysis tool that
provides visibility into the dynamic operation of an embed
-
ded system.
Second sources: Second sour
ces of a few NMOS versions of
the 68000 are Hitachi, Philips, and T
oshiba.
Motorola MCore
Motorola 68EC000
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