3/24/97 3-14 XA Memory Organization
An SFR address is always contained entirely within an instruction. The SFR address is always
encoded in the instruction providing the access, and there is no other way of addressing an SFR.
Details of access to external SFRs is determined by derivative implementation. Access to off-
chip SFRs is a reserved feature not implemented in the baseline XA. Consult derivative product
datasheets for details of external SFR access, e.g., timing.
3.7 Summary of Bit Addressing
Several sections of this chapter have described portions of the XA that are bit-addressable. There
are a total of 1024 addressable bits distributed in the XA architecture, chosen to make important
data structures immediately accessible via XA bit-processing instructions, specifically, all
registers in the register file, R0 through R7 (and R8 through R15 if implemented); directly
addressable RAM addresses 20h through 3Fh in the page currently specified by DS, and a
portion of the on-chip SFRs. Figure 3.15 summarizes all the bit-addressable portions of the XA.5
Figure 3.15 Bit addressing summary
bit space overlaps bytes...
start end
type
0
0FFh
100h
1FFh
200h
3FFh
registers
direct RAM
on-chip SFRs
R0
start end
R15
20h 3Fh
43Fh400h
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