Intel 8253 - Page 631

80C32/80C52
Rev. G (14 Jan. 97)
17
MATRA MHS
Serial Port Timing – Shift Register Mode (values in ns)
16 MHz 20 MHz 25 MHz 30 MHz 36 MHz 40 MHz 42 MHz 44 MHz
SYM-
BOL
PARAMETER min max min max min max min max min max min max min max min max
TXLXL Serial Port Clock Cycle Time 750 600 480 400 330 250 230 227
TQVXH Output Data Setup to Clock
Rising Edge
563 480 380 300 220 170 150 140
TXHQX Output Data Hold after Clock
Rising Edge
63 90 65 50 45 35 30 25
TXHDX Input Data Hold after Clock
Rising Edge
0 0 0 0 0 0 0 0
TXHDV Clock Rising Edge to Input
Data Valid
563 450 350 300 250 200 180 160
Shift Register Timing Waveforms