diagram above, several different types of hardware error conditions can trigger this interrupt
request. This line, unlike the IRQ lines, signal a hardware failure of some sort or a request from
the 8087 floating point processor and therefore it would be inappropriate to attach a normal
peripheral device to the NMI line. In a normal situation, the NMI enable line is always set,
meaning that if a device asserts an interrupt on one of these lines, the CPU will always receive it.
The NMI enable line is inactive only for diagnostic purposes.
The interrupt controller connects to the CPU directly via the INTR (interrupt) line. When one or
more devices are requesting an interrupt, the 8259A selects the highest priority device, as
mentioned, and encodes the corresponding vector number in one of its internal registers. It then
activates the INTR line. When the currently executing instruction finishes, the CPU checks the
status of the INTR line. If the line is active and the interrupt flag in the FLAGS register is set, the
CPU will process the interrupt. To signal to the interrupt controller that the CPU has recognized
the interrupt, it activates the INTA# (interrupt acknowledge) line. The bar over the top of the
signal name in the diagram (or the pound sign following it in the text) indicates that this signal
uses negative logic. This means that a value of zero (no voltage) means "true." As you see from
the diagram above, the CPU itself has no INTA# line. Instead, it negates (sets to negative logic
"true") three status lines, S0, S1, and S2. The lines connect to additional circuitry in the form of
the 8288 chip. When all three lines are zero, the 8388 sets its output line to zero as well, thus
indicating to the 8259A chip that the CPU has recognized the interrupt request. At this moment,
the 8259A "freezes" the priority by setting the ISR (In Service Register), so that if a device at the
same or lower priority device requests an interrupt before the CPU finishes processing the
current interrupt, the controller will not pass the new request on to the CPU until the end of the
exception processing state. Since the controller will normally activate the INTR line whenever
one of the IRQ lines is active, the CPU would continue to receive the interrupt request of the
device that it is already processing. The priority "freeze" ensures that the CPU recognizes an
interrupt only once.
An interesting feature of the 8259 family of interrupt controllers is that it is possible to cascade
multiple controllers to allow adding more interrupt priority levels and thus more devices.
Beginning with the 80286 family of processors, the machines have come standard with a pair of
controllers, thus allowing 15 different levels of interrupts. The diagram below shows the basic
connection scheme. Note that all of the interrupt levels from the slave controller have lower
priorities than that of the device connected to IRQ1, but higher than that of the device connected
to IRQ3.
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