SDA Operator’s Manual
PLL Setup
The "PLL Settings" dialog contains the controls to set the type and bandwidth of the digital PLL
used in the jitter, eye pattern, and bit error rate tests. The PLL bandwidth limits the response of
the recovered clock to high rate variations in the data rate. For example, a PLL bandwidth of 750
kHz will allow the recovered clock to track frequency variations below this rate, thereby removing
their effect from jitter and eye pattern measurements. The software PLL implemented in the SDA
allows you to choose among four types of PLL.
The selected PLL is applied to either the data stream under test or the selected clock source
when the PLL On control is checked. The PLL recovers a reference clock from the selected
source, which is used by all subsequent SDA measurements (jitter, eye pattern, and, with option
ASDA-J, bit error rate).
1. Place a check in the PLL On checkbox to enable it.
2. Touch inside the PLL Type field to select the type of PLL to be used in the clock recovery
function. The four choices are FC Golder, PCI Express, DVI, and Custom.
• FC Golden is the default selection and implements the “golden” PLL as defined in the
Fibrechannel specification. By default, the golden PLL is set to a cutoff frequency of
1/1667 times the bit rate of the signal under test. This ratio can be adjusted from 1/10 to
1/1e6.
• The PCI Express PLL uses a filter that approximates the PCI-SIG compliance
requirement. The PCI-SIG compliance procedure describes a processing algorithm that
measures the average bit rate over 3500 consecutive unit intervals (UI or bit intervals).
The 250 UI in the center of this 3500 UI window are then processed using the average bit
rate as a reference clock. The 3500 UI window is then shifted by some number of UI and
the process is repeated. Measurement continues until the end of the acquired data record
is reached. The PCI Express PLL selection in the SDA models the sliding 3500 UI clock
recovery and 250 UI processing windows using a digital low-pass filter whose cutoff
frequency is approximately 1.5 MHz.
• The DVI selection follows the requirements of the DVI (Digital Video Interactive) and
HDMI (High Definition Multimedia Interface) specifications. These specifications call out a
clock recovery function that has a single-pole PLL loop response with a cutoff of 4 MHz.
• The Custom selection allows you to select either a first or second order loop response.
The first order response allows you to select a pole frequency that sets the PLL cutoff,
and a zero frequency that must be higher than the pole frequency that limits the stop-
band attenuation.
SDA-OM-E Rev H 315
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