The first step in creating a clock signal is the creation of a digital phase detector. This is simply a
software component that measures the location in time at which the signal crosses a given
threshold value. Given the maximum sampling rate available, 20 GHz, interpolation is necessary
in most cases. Interpolation is automatically performed by the SDA. Interpolation is not performed
on the entire waveform; rather, only the points surrounding the threshold crossing are interpolated
for the measurement. A cubic interpolation is used, followed by a linear fit to the interpolated data,
to find the crossing point. This is shown in Figure 1.
Figure 1. SDA Threshold Crossing Algorithm
Clock recovery implementation in the SDA is shown in Figure 2. This algorithm generates time
values corresponding to a clock at the data rate. The computation follows variations in the data
stream being tested through the use of a feedback control loop that corrects each period of the
clock by adding a portion of the error between the recovered clock edge and the nearest data
edge.
Figure 2. Clock Recovery Implementation
366 SDA-OM-E Rev H
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