Commissioning and Diagnostics
6-24
ET 200S Distributed I/O System
EWA-4NEB 780602402-12
Evaluating hardware interrupts with STEP 7
In the event of a hardware interrupt, the CPU interrupts the processing of the user
program and processes the OB 40 hardware interrupt block instead.
The module channel that triggered the hardware interrupt is entered in the start
information of OB 40 in the OB40_POINT_ADDR variable. In the figures below you
will find the assignment to the bits of the local double word 8.
Hardware interrupts in:
2DI DC24V HF and 4DI DC24V HF electronic modules:
1
Bit no.
3130
29 28 27 26
LD 81
LB 8
LB 9
25 24
Rising edge: Channel 2
Rising edge: Channel 0
Rising edge: Channel 3
LB 11
0
1
Rising edge: Channel 1
11
LB 10
2DI
4DI
Figure 6-18 Start information of the OB 40: which event has triggered a process interrupt with digital input
modules
Hardware interrupts in the case of:
2AI U High Speed, 2AI I 2WIRE High Speed, and 2AI I 4WIRE High Speed
electronic modules:
1
Bit no.
3130 29 28 27 26
LD 8
1
LB 8
25 24
Lower limit value exceeded: Channel 0
Upper limit value exceeded: Channel 1
LB 11
0
1
LB 10
1
2322 21 20 19 18
1
LB 9
17 16
Lower limit value not met: Channel 0
Upper limit value exceeded: Channel 1
Figure 6-19 Start information of the OB 40: which event has triggered a process interrupt with analog
input modules
You will find a description of the OBs 40 in the System and Standard Functions
reference manual.
Triggering of an insert/remove module interrupt
Insert/remove module interrupts are supported in DPV1 operation. The CPU
interrupts the processing of the user program and processes the OB 83 diagnostic
block. The result that triggered the interrupt is added to the OB 83 start
information.