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Hioki 3153 - Page 175

Hioki 3153
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162
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10.1 RS-232C Interface
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Bit 7
PON
Power on flag.
When the power is turned on, or on recovery from a power cut, this
bit is set to 1.
Bit 6
Unused.
Bit 5
CME
Command error.
When a command which has been received contains a syntactic or
semantic error, this bit is set to 1.
The command is not supported by the 3153.
There is a mistake in a program header.
The number of data parameters is wrong.
The format of the parameters is wrong.
Bit 4
EXE
Execution error.
When for some reason a command which has been received cannot be
executed, this bit is set to 1.
The designated data value is outside the set range.
The designated data value is not acceptable.
Bit 3
DDE
Device dependent error.
When a command cannot be executed due to some cause other than a
command error, a query error, or an execution error, this bit is set to
1.
Execution is impossible due to an abnormality inside the 3153.
Bit 2
QYE
Query error.
This bit is set to 1 when a query error is detected by the output queue
control.
When the data overflows the output queue.
When data in the output queue has been lost.
Bit 1
Unused.
Bit 0
Unused.
Output Queue
Response messages accumulate in the output queue and are transmitted as
data and cleared.
The output queue is also cleared when the power is turned off and turned on
again.
The 3153 has an output queue of 300 bytes capacity. If the response
messages overflow this limit of 300 bytes, a query error is generated, and the
output queue is cleared.
Input Buffer
The 3153 has an input buffer of 300 bytes capacity. When more than 300
bytes of data are transmitted, when the buffer is full any subsequent bytes
received will be ignored.
Event Registers
The 3153 includes two 8-bit event registers. It is possible to determine the
status of the unit by reading these registers.
The event register is cleared in the following situations:
When a CLS command is executed.
When an event register query is executed. (ESR?
,
:ESR0?
)
When the unit is powered on.
(1) Standard event status register (SESR) bit assignments

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