SDA Operator’s Manual
Address Bus Characteristics (Refer to Figure):
• During every period of BCLK, 2 bits are sent or there's an idle state (high voltage on both
strobes and relevant data).
• Bit transfers occur in double multiples of bits only (2, 4, 6…).
• There's sampling of address bits on both falling and rising edges of ADSTB
• Falling edge (ASTB#) samples address bit 0
• Rising edge (ASTB#) samples address bit 1
Address Bus Timing Diagram ©Intel Corporation
SDA-OM-E Rev H 361
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