Panasonic FP0R - Page 283

15-21
FP0R (A: Available, N/A: Not available)
Address Name Description
Read-
ing
Writ-
ing
DT90014
Operation auxiliary
register for data shift
instruction
One shift-out hexadecimal digit is stored in bit
positions 0 to 3 when the data shift instruction,
F105 (BSR) or F106 (BSL) is executed. The
value can be read and written by executing F0
(MV) instruction.
A A
DT90015
Operation auxiliary
register for division
instruction
The divided remainder (16-bit) is stored in
DT90015 when the division instruction F32(%)
or F52(B%) instruction is executed. The
divided remainder (32-bit) is stored in
DT90015 and DT90016 when the division
instruction F33(D%) or F53(DB%) is
executed. The value can be read and written
by executing F0(MV) instruction.
A A
DT90016 A A
DT90017
Operation error
address (hold type)
After commencing operation, the address
where the first operation error occurred is
stored. Monitor the address using decimal
display.
A N/A
DT90018
Operation error
address (latest type)
The address where an operation error
occurred is stored. Each time an error occurs,
the new address overwrites the previous
address.
A N/A
DT90019
2.5 ms ring counter
Note1)
The data stored here is increased by one
every 2.5 ms. (H0 to HFFFF)
Difference between the values of the two
points (absolute value) x 2.5 ms = Elapsed
time between the two points.
A N/A
DT90020
10
µ
s ring counter
Note1) Note2)
The data stored here is increased by one
every 10.67 µs. (H0 to HFFFF)
Difference between the values of the two
points (absolute value) x 10.67 µs = Elapsed
time between the two points.
Note) The exact value is 10.67 µs.
A N/A
DT90021
Not used
-
N/A N/A
Note1) It is renewed once at the beginning of each one scan.
Note2) As DT90020 is renewed even if F0(MV), DT90020 and D instruction is being executed, it can be
used to measure the block time.