Instrument Function
R&S
®
SMBV100A
280Operating Manual 1407.6062.32 ─ 08
SCPI Command: BB:DM:CLOC:SYNC:MODE SLAV
4. Perform "Set Synchronization Settings".
SCPI Command: BB:DM:CLOC:SYNC:EXEC
5. Select "Trigger/Marker/Clock > Global Trigger/Clock/External Input Settings > Auto-
matic Delay Compensation" and adjust the "Slave Position in Chain" and "Cable
Length". Enable the automatic delay compensation.
Following parameters are set automatically:
● The "Reference Oscillator" source is set to external.
● The "Trigger Mode" is set to retrigger and the "Trigger Source" is set to external.
● The "Clock Source" is set to external.
The slave instrument receives the synchronization clock (including the trigger signal)
and the reference clock of the master one.
The "Synchronization State" parameter of the slave instrument displays whether the
synchronization is achieved or not.
Each of the slave instruments calculate and compensate the expected timing delay
caused by the used cables.
5.8.2.5 Control Signals
The following control signals are processed in the R&S SMBV:
●
"Burst Gate" for power ramping
●
"Level Attenuation" for power ramping
●
"CW" for controlling the CW (continuous wave) mode
The "CW" signal turns off digital modulation. The signal is output in unmodulated form.
In case of standards in which it is possible to switch between different modulation
modes, the signal is output only and cannot be supplied from an external source. In
such cases it indicates the modulation mode internally (standard GSM: signal high
(1) = modulation mode GMSK and signal low (0) = modulation mode 8PSK EDGE).
The CW control signal and the signals for power ramping are generated internally.
A dedicated internal "Control Data Editor" is provided for defining the control signals. This
editor with its intuitive graphical interface can be used to define and save control signals.
Definition by generating or editing a binary list is no longer necessary (though it is still
possible via the IEC bus).
A separate file with the file extension *.dm_iqc is created for each defined control signal
and held on the R&S Signal Generator hard disk.
If the "Component Data Editor" is used, the "Control Data Editor" is integrated with it. The
defined control data is not held separately, but stored with the data structure. This applies
both to signals of the Data Editor Realtime and the Data Editor Offline.
Power Ramping and Level Attenuation
In TDMA radio networks it is necessary to control the RF output signal envelope syn-
chronously for the purpose of digital modulation. The signals "Burst" Gate and "Lev Att"
are used for this. These signals are internally generated.
Baseband Signal - Baseband Block
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