Schweitzer Engineering Laboratories SEL-311C - Page 18

xvi List of Figures
SEL-311C Relay Instruction Manual Date Code 20060320
Figure 3.22 Levels 1 Through 4 Residual Ground Instantaneous/
Definite-Time Overcurrent Elements With Directional and Torque Control....................3.29
Figure 3.23 Levels 1 Through 4 Negative-Sequence Instantaneous/
Definite-Time Overcurrent Elements With Directional and Torque Control....................3.32
Figure 3.24 Phase Time-Overcurrent Element 51PT ...............................................................................3.34
Figure 3.25 Residual Ground Time-Overcurrent Element 51GT ............................................................3.37
Figure 3.26 Negative-Sequence Time-Overcurrent Element 51QT.........................................................3.38
Figure 3.27 Single-Phase and Three-Phase Voltage Elements.................................................................3.41
Figure 3.28 Phase-to-Phase and Sequence Voltage Elements..................................................................3.42
Figure 3.29 Channel V
S
Voltage Elements ..............................................................................................3.42
Figure 3.30 Synchronism Check Voltage Window and Slip Frequency Elements ..................................3.46
Figure 3.31 Synchronism Check Elements ..............................................................................................3.47
Figure 3.32 Angle Difference Between V
P
and V
S
Compensated
by Breaker Close Time (f
P
< f
S
and V
P
Shown as Reference in This Example) ..............3.51
Figure 3.33 Undervoltage Block for Frequency Elements.......................................................................3.55
Figure 3.34 Levels 1 Through 6 Frequency Elements .............................................................................3.56
Figure 4.1 Loss-of-Potential Logic ..........................................................................................................4.1
Figure 4.2 CCVT Transient Blocking Logic............................................................................................4.4
Figure 4.3 Load-Encroachment Logic With Example Settings ...............................................................4.5
Figure 4.4 Migration of Apparent Positive-Sequence Impedance for a Fault Condition.........................4.8
Figure 4.5 General Logic Flow of Directional Control
for Ground Distance and Residual Ground Overcurrent Elements.....................................4.9
Figure 4.6 Internal Enables (32QE and 32QGE) Logic
for Negative-Sequence Voltage-Polarized Directional Elements......................................4.11
Figure 4.7 Internal Enables (32VE and 32IE) Logic for Zero-Sequence
Voltage-Polarized and Channel IP Current-Polarized Directional Elements....................4.12
Figure 4.8 Best Choice Ground Directional Logic ................................................................................4.13
Figure 4.9 Negative-Sequence Voltage-Polarized Directional Element
for Ground Distance and Residual Ground Overcurrent Elements...................................4.14
Figure 4.10 Zero-Sequence Voltage-Polarized Directional Element
for Ground Distance and Residual Ground Overcurrent Elements...................................4.15
Figure 4.11 Channel IP Current-Polarized Directional Element
for Ground Distance and Residual Ground Overcurrent Elements...................................4.16
Figure 4.12 Ground Distance and Residual Ground Directional Logic...................................................4.16
Figure 4.13 General Logic Flow of Directional Control for
Negative-Sequence Phase Overcurrent and Phase Distance Elements .............................4.17
Figure 4.14 Negative-Sequence Voltage-Polarized
Directional Element for Phase Distance and Negative-Sequence Elements.....................4.19
Figure 4.15 Positive-Sequence Voltage Polarized Directional Element for Phase Distance Elements ...4.20
Figure 5.1 Trip Logic ...............................................................................................................................5.2
Figure 5.2 Minimum Trip Duration Timer Operation (See Bottom of Figure 5.1) .................................5.3
Figure 5.3 Three-Pole Open Logic (Top) and Switch-Onto-Fault Logic (Bottom).................................5.7
Figure 5.4 Communications-Assisted Tripping Scheme........................................................................5.10
Figure 5.5 Permissive Input Logic Routing to POTT Logic..................................................................5.14
Figure 5.6 POTT Logic ..........................................................................................................................5.16
Figure 5.7 Permissive Input Logic Routing to Trip Logic .....................................................................5.17
Figure 5.8 SEL-311C Connections to Communications Equipment
for a Two-Terminal Line POTT Scheme...........................................................................5.18
Figure 5.9 SEL-311C Connections to Communications Equipment
for a Three-Terminal Line POTT Scheme ........................................................................5.18
Figure 5.10 DCUB Logic.........................................................................................................................5.22
Figure 5.11 Unblocking Block Logic Routing to Trip Logic ..................................................................5.23
Figure 5.12 SEL-311C Connections to Communications Equipment
for a Two-Terminal Line DCUB Scheme (Setting ECOMM = DCUB1).........................5.23
Figure 5.13 SEL-311C Connections to Communications Equipment
for a Three-Terminal Line DCUB Scheme (Setting ECOMM = DCUB2).......................5.24
Figure 5.14 DCB Logic............................................................................................................................5.28