6.3
Date Code 20060320 Instruction Manual SEL-311C Relay
Close and Reclose Logic
Close Logic
The CLOSE command is included in the close logic in the factory settings:
CL = . . . + CC
Relay Word bit CC asserts for execution of the CLOSE Command. See CLO
Command (Close Breaker) on page 10.34 for more information on the
CLOSE Command. More discussion follows later on the factory settings for
setting CL.
If a user wants to supervise the CLOSE command with optoisolated input
IN106, the following addition is made:
CL = . . . + CC * IN106
With this setting, the CLOSE command can provide a close only if
optoisolated input IN106 is asserted. This is just one CLOSE command
supervision example—many variations are possible.
Unlatch Close
If the CLOSE Relay Word bit is asserted at logical 1, it stays asserted at
logical 1 until one of the following occurs:
➤ The unlatch close condition asserts (ULCL = logical 1).
➤ The circuit breaker closes (52A = logical 1).
➤ The reclose initiation condition (79RI) makes a rising edge
(logical 0 to logical 1) transition.
➤ The Close Failure Timer times out (Relay Word bit CF = 1).
The Close Failure Timer is inoperative if setting CFD = OFF.
Factory
Settings Example
The factory settings for the close logic SELOGIC control equation settings are:
52A = IN101
CL = CC
ULCL = TRIP
The factory setting for the Close Failure Timer setting is:
CFD = 60.00 cycles
See Other Settings on page SET.14 for setting ranges.
Set Close
If the Reclosing Relay Open Interval Time-Out logic input at the top of
Figure 6.1 is ignored (reclosing is discussed in detail in a following
subsection), then SEL
OGIC control equation setting CL is the only logic input
that can set the CLOSE Relay Word bit.
In SEL
OGIC control equation setting CL = CC, Relay Word bit CC asserts for
execution of the CLOSE Command. See CLO Command (Close Breaker) on
page 10.34 for more information on the CLOSE Command.
Unlatch Close
SELOGIC control equation setting ULCL is usually set with the TRIP Relay
Word bit. This prevents the CLOSE Relay Word bit from being asserted any
time the TRIP Relay Word bit is asserted (TRIP takes priority). See Trip Logic
on page 5.1.