Texas Instruments TMS320C6455 User Manual

TMS320C6455
SPRS276M –MAY 2005–REVISED MARCH 2012 www.ti.com
Table 7-8. EDMA3 Transfer Controller 2 Registers (continued)
HEX ADDRESS RANGE ACRONYM REGISTER NAME
02A3 03C8 DFCNT3 Destination FIFO Count Register 3
02A3 03CC DFDST3 Destination FIFO Destination Address Register 3
02A3 03D0 DFBIDX3 Destination FIFO BIDX Register 3
02A3 03D4 DFMPPRXY3 Destination FIFO Memory Protection Proxy Register 3
02A3 03D8 - 02A3 7FFF - Reserved
Table 7-9. EDMA3 Transfer Controller 3 Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
02A3 8000 PID Peripheral Identification Register
02A3 8004 TCCFG EDMA3TC Configuration Register
02A3 8008 - 02A3 80FC - Reserved
02A3 8100 TCSTAT EDMA3TC Channel Status Register
02A3 8104 - 02A3 811C - Reserved
02A3 8120 ERRSTAT Error Register
02A3 8124 ERREN Error Enable Register
02A3 8128 ERRCLR Error Clear Register
02A3 812C ERRDET Error Details Register
02A3 8130 ERRCMD Error Interrupt Command Register
02A3 8134 - 02A3 813C - Reserved
02A3 8140 RDRATE Read Rate Register
02A3 8144 - 02A3 823C - Reserved
02A3 8240 SAOPT Source Active Options Register
02A3 8244 SASRC Source Active Source Address Register
02A3 8248 SACNT Source Active Count Register
02A3 824C SADST Source Active Destination Address Register
02A3 8250 SABIDX Source Active Source B-Index Register
02A3 8254 SAMPPRXY Source Active Memory Protection Proxy Register
02A3 8258 SACNTRLD Source Active Count Reload Register
02A3 825C SASRCBREF Source Active Source Address B-Reference Register
02A3 8260 SADSTBREF Source Active Destination Address B-Reference Register
02A3 8264 - 02A3 827C - Reserved
02A3 8280 DFCNTRLD Destination FIFO Set Count Reload
02A3 8284 DFSRCBREF Destination FIFO Set Destination Address B Reference Register
02A3 8288 DFDSTBREF Destination FIFO Set Destination Address B Reference Register
02A3 828C - 02A3 82FC - Reserved
02A3 8300 DFOPT0 Destination FIFO Options Register 0
02A3 8304 DFSRC0 Destination FIFO Source Address Register 0
02A3 8308 DFCNT0 Destination FIFO Count Register 0
02A3 830C DFDST0 Destination FIFO Destination Address Register 0
02A3 8310 DFBIDX0 Destination FIFO BIDX Register 0
02A3 8314 DFMPPRXY0 Destination FIFO Memory Protection Proxy Register 0
02A3 8318 - 02A3 833C - Reserved
02A3 8340 DFOPT1 Destination FIFO Options Register 1
02A3 8344 DFSRC1 Destination FIFO Source Address Register 1
02A3 8348 DFCNT1 Destination FIFO Count Register 1
02A3 834C DFDST1 Destination FIFO Destination Address Register 1
02A3 8350 DFBIDX1 Destination FIFO BIDX Register 1
118 C64x+ Peripheral Information and Electrical Specifications Copyright © 2005–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TMS320C6455

Texas Instruments TMS320C6455 Specifications

General

Clock Speed	1.0 GHz
Core Count	1
On-Chip RAM	Yes
Data Width	32-bit
Data Bus Width	64-bit
Operating Voltage	1.2 V
I/O Voltage	3.3 V
Instruction Set	TMS320C64x+
Memory	DDR2
Package Type	BGA
External Memory Interface	EMIF
Interfaces	I2C, SPI

Summary

1 Features

2 Device Overview

2.1 Device Characteristics

2.2 CPU (DSP Core) Description

Details the C64x+ CPU core, functional units, register files, and data paths.

2.3 Memory Map Summary

2.4 Boot Sequence

Explains the process of initializing the DSP's memory and registers at reset.

3 Device Configuration

3.1 Device Configuration at Device Reset

Details configuration pins (AEA, ABA, PCI_EN) for boot mode, clock source, and endianness.

3.2 Peripheral Configuration at Device Reset

3.4 Device State Control Registers

3.5 Device Status Register Description

5 C64x+ Megamodule

5.1 Memory Architecture

Describes the L2, L1P, and L1D memory configurations and sizes.

5.2 Memory Protection

5.3 Bandwidth Management

6 Device Operating Conditions

6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)

Specifies stress ratings for voltage, temperature, and other conditions beyond which damage may occur.

6.2 Recommended Operating Conditions

Lists recommended operating ranges for supply voltages, input/output, and temperatures.

6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)

Details electrical characteristics under specified operating conditions.

7 C64x+ Peripheral Information and Electrical Specifications

7.1 Parameter Information

7.3 Power Supplies

Covers power supply sequencing, decoupling, and power-down operation.

7.4 Enhanced Direct Memory Access (EDMA3) Controller

Details EDMA3 features like transfer dimensions, PaRAM entries, and DMA channels.

7.5 Interrupts

7.6 Reset Controller

Describes different reset types (POR, Warm, Max, System, CPU) and their effects.

7.7 PLL1 and PLL1 Controller

Details PLL1 controller operation, clocks, and registers for frequency synthesis.

7.8 PLL2 and PLL2 Controller

Describes PLL2 controller operation, clocks, and registers for EMAC and DDR2 memory.

7.9 DDR2 Memory Controller

Explains DDR2 interface, device-specific information, and memory topologies.

7.10 External Memory Interface A (EMIFA)

Covers EMIFA interface capabilities for various external devices and timing.

7.11 I2C Peripheral

Describes the I2C module, its features, and device-specific information.

7.12 Host-Port Interface (HPI) Peripheral

7.13 Multichannel Buffered Serial Port (McBSP)

7.14 Ethernet MAC (EMAC)

Describes EMAC module, interface modes (MII, RMII, GMII, RGMII), and control modules.

7.15 Timers

7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2)

7.17 Enhanced Turbo Decoder Coprocessor (TCP2)

7.18 Peripheral Component Interconnect (PCI)

7.20 Serial RapidIO (SRIO) Port

7.22 Emulation Features and Capability