TMS320C6455
SPRS276M –MAY 2005–REVISED MARCH 2012
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7.22.3 IEEE 1149.1 JTAG
7.22.3.1 JTAG Device-Specific Information
7.22.3.1.1 IEEE 1149.1 JTAG Compatibility Statement
For maximum reliability, the C6455 DSP includes an internal pulldown (IPD) on the TRST pin to ensure
that TRST will always be asserted upon power up and the DSP's internal emulation logic will always be
properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive
TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of
an external pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the
DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan
operations.
7.22.4 JTAG Peripheral Register Descriptions
7.22.5 JTAG Electrical Data/Timing
Table 7-116. Timing Requirements for JTAG Test Port
(see Figure 7-79)
-720
-850
A-1000/-1000
NO. UNIT
-1200
MIN MAX
1 t
c(TCK)
Cycle time, TCK 35 ns
3 t
su(TDIV-TCKH)
Setup time, TDI/TMS/TRST valid before TCK high 6 ns
4 t
h(TCKH-TDIV)
Hold time, TDI/TMS/TRST valid after TCK high 9 ns
Table 7-117. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 7-79)
-720
-850
A-1000/-1000
NO. PARAMETER UNIT
-1200
MIN MAX
2 t
d(TCKL-TDOV)
Delay time, TCK low to TDO valid -3 11 ns
Figure 7-79. JTAG Test-Port Timing
248 C64x+ Peripheral Information and Electrical Specifications Copyright © 2005–2012, Texas Instruments Incorporated
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