TMS320C6455
SPRS276M –MAY 2005–REVISED MARCH 2012
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7.5 Interrupts
7.5.1 Interrupt Sources and Interrupt Controller
The CPU interrupts on the C6455 device are configured through the C64x+ Megamodule Interrupt
Controller. The interrupt controller allows for up to 128 system events to be programmed to any of the
twelve CPU interrupt inputs (CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced
emulation logic. The 128 system events consist of both internally-generated events (within the
megamodule) and chip-level events. Table 7-10 shows the mapping of system events. For more
information on the Interrupt Controller, see the TMS320C64x+ Megamodule Reference Guide (literature
number SPRU871).
Table 7-10. C6455 System Event Mapping
EVENT NUMBER INTERRUPT EVENT DESCRIPTION
0
(1)
EVT0 Output of event combiner 0 in interrupt controller, for events 1 - 31.
1
(1)
EVT1 Output of event combiner 1 in interrupt controller, for events 32 - 63.
2
(1)
EVT2 Output of event combiner 2 in interrupt controller, for events 64 - 95.
Output of event combiner 3 in interrupt controller, for events 96 -
3
(1)
EVT3
127.
Reserved. These system events are not connected and, therefore,
4 - 8 Reserved
not used.
EMU interrupt for:
1. Host scan access
9
(1)
EMU_DTDMA
2. DTDMA transfer complete
3. AET interrupt
10 None This system event is not connected and, therefore, not used.
11
(1)
EMU_RTDXRX EMU real-time data exchange (RTDX) receive complete
12
(1)
EMU_RTDXTX EMU RTDX transmit complete
13
(1)
IDMA0 IDMA channel 0 interrupt
14
(1)
IDMA1 IDMA channel 1 interrupt
15 DSPINT HPI/PCI-to-DSP interrupt
16 I2CINT I2C interrupt
17 MACINT Ethernet MAC interrupt
18 AEASYNCERR EMIFA error interrupt
Reserved. This system event is not connected and, therefore, not
19 Reserved
used.
20 INTDST0 RapidIO interrupt 0
21 INTDST1 RapidIO interrupt 1
22 INTDST4 RapidIO interrupt 4
Reserved. This system event is not connected and, therefore, not
23 Reserved
used.
24 EDMA3CC_GINT EDMA3 channel global completion interrupt
Reserved. These system events are not connected and, therefore,
25 - 31 Reserved
not used.
32 VCP2_INT VCP2 error interrupt
33 TCP2_INT TCP2 error interrupt
Reserved. These system events are not connected and, therefore,
34 - 35 Reserved
not used.
36 UINT UTOPIA interrupt
Reserved. These system events are not connected and, therefore,
37 - 39 Reserved
not used.
40 RINT0 McBSP0 receive interrupt
(1) This system event is generated from within the C64x+ megamodule.
120 C64x+ Peripheral Information and Electrical Specifications Copyright © 2005–2012, Texas Instruments Incorporated
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