TMS320C6455
SPRS276M –MAY 2005–REVISED MARCH 2012
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7.13.3 McBSP Electrical Data/Timing
Table 7-59. Timing Requirements for McBSP
(1)
(see Figure 7-52)
-720
-850
A-1000/-1000
NO. UNIT
-1200
MIN MAX
2 t
c(CKRX)
Cycle time, CLKR/X CLKR/X ext 6P or 10
(2) (3)
ns
3 t
w(CKRX)
Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext 0.5t
c(CKRX)
- 1
(4)
ns
CLKR int 9
5 t
su(FRH-CKRL)
Setup time, external FSR high before CLKR low ns
CLKR ext 1.3
CLKR int 6
6 t
h(CKRL-FRH)
Hold time, external FSR high after CLKR low ns
CLKR ext 3
CLKR int 8
7 t
su(DRV-CKRL)
Setup time, DR valid before CLKR low ns
CLKR ext 0.9
CLKR int 3
8 t
h(CKRL-DRV)
Hold time, DR valid after CLKR low ns
CLKR ext 3.1
CLKX int 9
10 t
su(FXH-CKXL)
Setup time, external FSX high before CLKX low ns
CLKX ext 1.3
CLKX int 6
11 t
h(CKXL-FXH)
Hold time, external FSX high after CLKX low ns
CLKX ext 3
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
188 C64x+ Peripheral Information and Electrical Specifications Copyright © 2005–2012, Texas Instruments Incorporated
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