RMREFCLK
(Input)
1
2
3
3
4
5
RMRXD1-RMRXD0,
RMCRSDV,
RMRXER (Inputs)
TMS320C6455
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SPRS276M –MAY 2005–REVISED MARCH 2012
Table 7-83. Timing Requirements for EMAC RMII Input Receive for 100 Mbps
(1)
(see Figure 7-67)
-720
-850
A-1000/-1000
NO. UNIT
-1200
MIN MAX
t
su(RMRXD-
Setup time, receive selected signals valid before RMREFCLK (at DSP)
1 4.0 ns
RMREFCLK)
high/low
t
h(RMREFCLK-
Hold time, receive selected signals valid after RMREFCLK (at DSP)
2 2.0 ns
RMRXD)
high/low
(1) For RMII, receive selected signals include: RMRXD[1:0], RMRXER, and RMCRSDV.
Figure 7-67. EMAC Receive Interface Timing [RMII Operation]
Copyright © 2005–2012, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications 211
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