TMS320C6455
SPRS276M –MAY 2005–REVISED MARCH 2012
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7.7.3.3 PLL Pre-Divider Control Register
The PLL pre-divider control register (PREDIV) is shown in Figure 7-13 and described in Table 7-21.
31 16
Reserved
R-0
15 14 5 4 0
PREDEN Reserved RATIO
R/W-1 R-0 R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-13. PLL Pre-Divider Control Register (PREDIV) [Hex Address: 029A 0114]
Table 7-21. PLL Pre-Divider Control Register (PREDIV) Field Descriptions
Bit Field Value Description
31:16 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
15 PREDEN Pre-divider enable bit.
0 Pre-divider is disabled. No clock output.
1 Pre-divider is enabled.
14:5 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
4:0 RATIO 0-1Fh Divider ratio bits.
0 ÷1. Divide frequency by 1.
1h ÷2. Divide frequency by 2.
2h ÷3. Divide frequency by 3.
3h-1Fh Reserved, do not use.
138 C64x+ Peripheral Information and Electrical Specifications Copyright © 2005–2012, Texas Instruments Incorporated
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