MDIO
EMAC
10/100/1000
Serial
RapidIO
DDR2
Mem Ctlr
64
C6455
HI
VCP2
I2C
16
RMGII
(D)
L2Cache
Memory
2048K
Bytes
TCP2
HPI (32/16)
(B)
DDR2 SDRAM
32
LO
Timer1
(C)
PLL2 and
PLL2
Controller
(D)
GMII
RMII
MII
Primary
Switched
Central
Resource
L2 Memory Controller
(Memory Protect/
Bandwidth Mgmt)
System
C64x+ DSP Core
Data Path B
B Register File
B31−B16
B15−B0
Instruction Fetch
Data Path A
A Register File
A31−A16
A15−A0
.L1
.S1
.M1
xx
xx
.D1 .D2
.M2
xx
xx
.S2
.L2
Internal DMA
(IDMA)
M
e
g
a
m
o
d
u
l
e
L1P Memory Controller (Memory Protect/Bandwidth Mgmt)
Instruction
Decode
16-/32-bit
Instruction Dispatch
Power Control
L1D Memory Controller (Memory Protect/Bandwidth Mgmt)
Interrupt and Exception Controller
EMIFA
HI
LO
Timer1
(C)
EDMA 3.0
Secondary
Switched Central
Resource
PLL1 and
PLL1
Controller
Device
Configuration
Logic
Boot Configuration
L1D SRAM/Cache
2-Way Set-Associative
32K Bytes Total
L1P SRAM/Cache Direct-Mapped
32K Bytes
L2 ROM
32K
Bytes
(E)
Control Registers
SPLOOP Buffer
In-Circuit Emulation
PCI66
(B)
UTOPIA
(B)
GPIO16
(B)
McBSP1
(A)
McBSP0
(A)
SBSRAM
ZBT SRAM
SRAM
ROM/FLASH
I/O Devices
A. McBSPs: Framing Chips - H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs.
B. The PCI peripheral pins are muxed with some of the HPI peripheral pins and the UTOPIA address pins.
For more detailed information, see the section.
C. Each of the TIMER peripherals (TIMER1 and TIMER0) is configurable as a 64-bit general-purpose timer, dual 32-bit general-purpose timers,
or a watchdog timer.
D. The PLL2 controller also generates clocks for the EMAC.
E. When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz.
Device Configuration
TMS320C6455
SPRS276M –MAY 2005–REVISED MARCH 2012
www.ti.com
1.3 Functional Block Diagram
Figure 1-2 shows the functional block diagram of the C6455 device.
Figure 1-2. Functional Block Diagram
4 Features Copyright © 2005–2012, Texas Instruments Incorporated
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Product Folder Link(s): TMS320C6455
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