Texas Instruments TMS320C6455 User Manual

TMS320C6455
www.ti.com SPRS276M –MAY 2005–REVISED MARCH 2012
Table 7-112. RapidIO Control Registers (continued)
HEX ADDRESS RANGE ACRONYM REGISTER NAME
02D0 0940 - 02D0 09FC - Reserved
RapidIO Peripheral-Specific Registers
02D0 1000 RIO_DEV_ID Device Identity CAR
02D0 1004 RIO_DEV_INFO Device Information CAR
02D0 1008 RIO_ASBLY_ID Assembly Identity CAR
02D0 100C RIO_ASBLY_INFO Assembly Information CAR
02D0 1010 RIO_PE_FEAT Processing Element Features CAR
02D0 1014 - Reserved
02D0 1018 RIO_SRC_OP Source Operations CAR
02D0 101C RIO_DEST_OP Destination Operations CAR
02D0 1020 - 02D0 1048 - Reserved
02D0 104C RIO_PE_LL_CTL Processing Element Logical Layer Control CSR
02D0 1050 - 02D0 1054 - Reserved
02D0 1058 RIO_LCL_CFG_HBAR Local Configuration Space Base Address 0 CSR
02D0 105C RIO_LCL_CFG_BAR Local Configuration Space Base Address 1 CSR
02D0 1060 RIO_BASE_ID Base Device ID CSR
02D0 1064 - Reserved
02D0 1068 RIO_HOST_BASE_ID_LOCK Host Base Device ID Lock CSR
02D0 106C RIO_COMP_TAG Component Tag CSR
02D0 1070 - 02D0 10FC - Reserved
RapidIO Extended Features - LP Serial Registers
02D0 1100 RIO_SP_MB_HEAD 1x/4x LP Serial Port Maintenance Block Header
02D0 1104 - 02D0 1118
02D0 1120 RIO_SP_LT_CTL Port Link Time-Out Control CSR
02D0 1124 RIO_SP_RT_CTL Port Response Time-Out Control CSR
02D0 1128 - 02D0 1138 - Reserved
02D0 113C RIO_SP_GEN_CTL Port General Control CSR
02D0 1140 RIO_SP0_LM_REQ Port 0 Link Maintenance Request CSR
02D0 1144 RIO_SP0_LM_RERIO_SP Port 0 Link Maintenance Response CSR
02D0 1148 RIO_SP0_ACKID_STAT Port 0 Local Acknowledge ID Status CSR
02D0 114C - 02D0 1154 - Reserved
02D0 1158 RIO_SP0_ERR_STAT Port 0 Error and Status CSR
02D0 115C RIO_SP0_CTL Port 0 Control CSR
02D0 1160 RIO_SP1_LM_REQ Port 1 Link Maintenance Request CSR
02D0 1164 RIO_SP1_LM_RERIO_SP Port 1 Link Maintenance Response CSR
02D0 1168 RIO_SP1_ACKID_STAT Port 1 Local Acknowledge ID Status CSR
02D0 116C - 02D0 1174 - Reserved
02D0 1178 RIO_SP1_ERR_STAT Port 1 Error and Status CSR
02D0 117C RIO_SP1_CTL Port 1 Control CSR
02D0 1180 RIO_SP2_LM_REQ Port 2 Link Maintenance Request CSR
02D0 1184 RIO_SP2_LM_RERIO_SP Port 2 Link Maintenance Response CSR
02D0 1188 RIO_SP2_ACKID_STAT Port 2 Local Acknowledge ID Status CSR
02D0 118C - 02D0 1194 - Reserved
02D0 1198 RIO_SP2_ERR_STAT Port 2 Error and Status CSR
02D0 119C RIO_SP2_CTL Port 2 Control CSR
02D0 11A0 RIO_SP3_LM_REQ Port 3 Link Maintenance Request CSR
02D0 11A4 RIO_SP3_LM_RERIO_SP Port 3 Link Maintenance Response CSR
Copyright © 2005–2012, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications 241
Submit Documentation Feedback
Product Folder Link(s): TMS320C6455

Texas Instruments TMS320C6455 Specifications

General

Clock Speed	1.0 GHz
Core Count	1
On-Chip RAM	Yes
Data Width	32-bit
Data Bus Width	64-bit
Operating Voltage	1.2 V
I/O Voltage	3.3 V
Instruction Set	TMS320C64x+
Memory	DDR2
Package Type	BGA
External Memory Interface	EMIF
Interfaces	I2C, SPI

Summary

1 Features

2 Device Overview

2.1 Device Characteristics

2.2 CPU (DSP Core) Description

Details the C64x+ CPU core, functional units, register files, and data paths.

2.3 Memory Map Summary

2.4 Boot Sequence

Explains the process of initializing the DSP's memory and registers at reset.

3 Device Configuration

3.1 Device Configuration at Device Reset

Details configuration pins (AEA, ABA, PCI_EN) for boot mode, clock source, and endianness.

3.2 Peripheral Configuration at Device Reset

3.4 Device State Control Registers

3.5 Device Status Register Description

5 C64x+ Megamodule

5.1 Memory Architecture

Describes the L2, L1P, and L1D memory configurations and sizes.

5.2 Memory Protection

5.3 Bandwidth Management

6 Device Operating Conditions

6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)

Specifies stress ratings for voltage, temperature, and other conditions beyond which damage may occur.

6.2 Recommended Operating Conditions

Lists recommended operating ranges for supply voltages, input/output, and temperatures.

6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)

Details electrical characteristics under specified operating conditions.

7 C64x+ Peripheral Information and Electrical Specifications

7.1 Parameter Information

7.3 Power Supplies

Covers power supply sequencing, decoupling, and power-down operation.

7.4 Enhanced Direct Memory Access (EDMA3) Controller

Details EDMA3 features like transfer dimensions, PaRAM entries, and DMA channels.

7.5 Interrupts

7.6 Reset Controller

Describes different reset types (POR, Warm, Max, System, CPU) and their effects.

7.7 PLL1 and PLL1 Controller

Details PLL1 controller operation, clocks, and registers for frequency synthesis.

7.8 PLL2 and PLL2 Controller

Describes PLL2 controller operation, clocks, and registers for EMAC and DDR2 memory.

7.9 DDR2 Memory Controller

Explains DDR2 interface, device-specific information, and memory topologies.

7.10 External Memory Interface A (EMIFA)

Covers EMIFA interface capabilities for various external devices and timing.

7.11 I2C Peripheral

Describes the I2C module, its features, and device-specific information.

7.12 Host-Port Interface (HPI) Peripheral

7.13 Multichannel Buffered Serial Port (McBSP)

7.14 Ethernet MAC (EMAC)

Describes EMAC module, interface modes (MII, RMII, GMII, RGMII), and control modules.

7.15 Timers

7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2)

7.17 Enhanced Turbo Decoder Coprocessor (TCP2)

7.18 Peripheral Component Interconnect (PCI)

7.20 Serial RapidIO (SRIO) Port

7.22 Emulation Features and Capability