Bit(n-1) (n-2) (n-3)
Bit 0 Bit(n-1) (n-2) (n-3)
14
12
11
10
9
3
3
2
8
7
6
5
4
4
3
1
3
2
CLKS
CLKR
FSR (int)
FSR (ext)
DR
CLKX
FSX (int)
FSX (ext)
FSX (XDATDLY=00b)
DX
13
(A)
13
(A)
TMS320C6455
SPRS276M –MAY 2005–REVISED MARCH 2012
www.ti.com
A. Parameter No. 13 applies to the first data bit only when XDATDLY ≠ 0.
B. The CLKS signal is shared by both McBSP0 and McBSP1 on this device.
Figure 7-52. McBSP Timing
(B)
190 C64x+ Peripheral Information and Electrical Specifications Copyright © 2005–2012, Texas Instruments Incorporated
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