Texas Instruments TMS320C6455 User Manual

25
23
19
18
22
27
20
21
17
18
28
Stop Start Repeated
Start
Stop
SDA
SCL
16
26 24
TMS320C6455
www.ti.com SPRS276M –MAY 2005–REVISED MARCH 2012
Table 7-53. Switching Characteristics for I2C Timings
(1)
(see Figure 7-43)
-720
-850
A-1000/-1000
NO. PARAMETER UNIT
-1200
STANDARD MODE FAST MODE
MIN MAX MIN MAX
16 t
c(SCL)
Cycle time, SCL 10 2.5 μs
Delay time, SCL high to SDA low (for a
17 t
d(SCLH-SDAL)
4.7 0.6 μs
repeated START condition)
Delay time, SDA low to SCL low (for a START
18 t
d(SDAL-SCLL)
4 0.6 μs
and a repeated START condition)
19 t
w(SCLL)
Pulse duration, SCL low 4.7 1.3 μs
20 t
w(SCLH)
Pulse duration, SCL high 4 0.6 μs
21 t
d(SDAV-SDLH)
Delay time, SDA valid to SCL high 250 100 ns
Valid time, SDA valid after SCL low
22 t
v(SDLL-SDAV)
0 0 0.9 μs
(for I2C bus devices)
Pulse duration, SDA high between STOP and
23 t
w(SDAH)
4.7 1.3 μs
START conditions
24 t
r(SDA)
Rise time, SDA 1000 20 + 0.1C
b
(2)
300 ns
25 t
r(SCL)
Rise time, SCL 1000 20 + 0.1C
b
(2)
300 ns
26 t
f(SDA)
Fall time, SDA 300 20 + 0.1C
b
(2)
300 ns
27 t
f(SCL)
Fall time, SCL 300 20 + 0.1C
b
(2)
300 ns
Delay time, SCL high to SDA high (for STOP
28 t
d(SCLH-SDAH)
4 0.6 μs
condition)
29 C
p
Capacitance for each I2C pin 10 10 pF
(1) C
b
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
(2) C
b
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
Figure 7-43. I2C Transmit Timings
Copyright © 2005–2012, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications 173
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Texas Instruments TMS320C6455 Specifications

General

Brand	Texas Instruments
Model	TMS320C6455
Category	Signal Processors
Language	English