TMS320C6455
www.ti.com
SPRS276M –MAY 2005–REVISED MARCH 2012
1 Features ................................................... 1 5.7 C64x+ Megamodule Register Descriptions ........ 89
1.1 CTZ/GTZ/ZTZ BGA Package (Bottom View) ........ 2 6 Device Operating Conditions ....................... 97
6.1 Absolute Maximum Ratings Over Operating Case
1.2 Description ........................................... 2
Temperature Range (Unless Otherwise Noted) .... 97
1.3 Functional Block Diagram ........................... 4
6.2 Recommended Operating Conditions .............. 97
Revision History .............................................. 6
6.3 Electrical Characteristics Over Recommended
2 Device Overview ........................................ 7
Ranges of Supply Voltage and Operating Case
2.1 Device Characteristics ............................... 7
Temperature (Unless Otherwise Noted) ........... 99
2.2 CPU (DSP Core) Description ........................ 8
7 C64x+ Peripheral Information and Electrical
Specifications ......................................... 101
2.3 Memory Map Summary ............................ 11
7.1 Parameter Information ............................ 101
2.4 Boot Sequence ..................................... 13
7.2 Recommended Clock and Control Signal Transition
2.5 Pin Assignments .................................... 16
Behavior ........................................... 103
2.6 Signal Groups Description ......................... 20
7.3 Power Supplies .................................... 103
2.7 Terminal Functions ................................. 26
7.4 Enhanced Direct Memory Access (EDMA3)
2.8 Development ........................................ 51
Controller .......................................... 105
3 Device Configuration ................................. 55
7.5 Interrupts .......................................... 120
3.1 Device Configuration at Device Reset ............. 55
7.6 Reset Controller ................................... 124
3.2 Peripheral Configuration at Device Reset .......... 57
7.7 PLL1 and PLL1 Controller ......................... 132
3.3 Peripheral Selection After Device Reset ........... 58
7.8 PLL2 and PLL2 Controller ......................... 147
3.4 Device State Control Registers ..................... 60
7.9 DDR2 Memory Controller ......................... 156
3.5 Device Status Register Description ................ 71
7.10 External Memory Interface A (EMIFA) ............ 158
3.6 JTAG ID (JTAGID) Register Description ........... 73
7.11 I2C Peripheral ..................................... 169
3.7 Pullup/Pulldown Resistors .......................... 74
7.12 Host-Port Interface (HPI) Peripheral .............. 174
3.8 Configuration Examples ............................ 74
7.13 Multichannel Buffered Serial Port (McBSP) ....... 185
4 System Interconnect .................................. 77
7.14 Ethernet MAC (EMAC) ............................ 199
4.1 Internal Buses, Bridges, and Switch Fabrics ....... 77
7.15 Timers ............................................. 217
4.2 Data Switch Fabric Connections ................... 78
7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2) . 219
4.3 Configuration Switch Fabric ........................ 80
7.17 Enhanced Turbo Decoder Coprocessor (TCP2) .. 220
4.4 Bus Priorities ....................................... 82
7.18 Peripheral Component Interconnect (PCI) ........ 222
5 C64x+ Megamodule ................................... 83
7.19 UTOPIA ........................................... 229
5.1 Memory Architecture ............................... 83
7.20 Serial RapidIO (SRIO) Port ....................... 233
5.2 Memory Protection ................................. 85
7.21 General-Purpose Input/Output (GPIO) ............ 245
5.3 Bandwidth Management ............................ 86
7.22 Emulation Features and Capability ............... 247
5.4 Power-Down Control ............................... 87
8 Mechanical Data ...................................... 249
5.5 Megamodule Resets ............................... 87
8.1 Thermal Data ...................................... 249
5.6 Megamodule Revision .............................. 88
8.2 Packaging Information ............................ 249
Copyright © 2005–2012, Texas Instruments Incorporated Contents 5
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