Texas Instruments TMS320C6455 User Manual

PLLV2
PLL2
SYSCLK2(FromPLL1Controller)
SYSCLK1
DDR2
Memory
Controller
EMAC
CLKIN2
(B)(C)
C162
560 pF
EMIFilter
+1.8V
C161
0.1 Fm
PLL2Controller
TMS320C6455DSP
PLLM
x20
/2
1
0
/x
(A)
1
SYSREFCLK
SYSCLK3(FromPLL1Controller)
PLLREF PLLOUT
DIVIDERD1
TMS320C6455
www.ti.com SPRS276M –MAY 2005–REVISED MARCH 2012
7.8 PLL2 and PLL2 Controller
The secondary PLL controller generates interface clocks for the Ethernet media access controller (EMAC)
and the DDR2 memory controller.
As shown in Figure 7-23, the PLL2 controller features a PLL multiplier controller and one divider (D1). The
PLL multiplier is fixed to a x20 multiplier rate and the divider D1 can be programmed to a ÷2 or ÷5 mode.
PLL2 power is supplied externally via the PLL2 power supply (PLLV2). An external PLL filter circuit must
be added to PLLV2 as shown in Figure 7-23. The 1.8-V supply for the EMI filter must be from the same
1.8-V power plane supplying the I/O power-supply pin, DV
DD18
. TI requires EMI filter manufacturer Murata,
part number NFM18CC222R1C3 or NFM18CC223R1C3.
All PLL external components (C161, C162, and the EMI Filter) should be placed as close to the C64x+
DSP device as possible. For the best performance, TI requires that all the PLL external components be on
a single side of the board without jumpers, switches, or components other than the ones shown. For
reduced PLL jitter, maximize the spacing between switching signals and the PLL external components
(C161, C162, and the EMI Filter). The minimum CLKIN2 rise and fall times should also be observed. For
the input clock timing requirements, see Section 7.8.4, PLL2 Controller Input Clock Electrical Data/Timing.
CAUTION
The PLL controller module as described in the TMS320C645x DSP Software-
Programmable Phase-Locked Loop (PLL) Controller User's Guide (literature number
SPRUE56) includes a superset of features, some of which are not supported on the
C6455 DSP. The following sections describe the features that are supported; it should
be assumed that any feature not included in these sections is not supported by the
C6455 DSP.
A. /x must be programmed to /2 for GMII (default) and to /5 for RGMII.
B. If EMAC is enabled with RGMII, or GMII, CLKIN2 frequency must be 25 MHz.
C. CLKIN2 is a 3.3-V signal.
Figure 7-23. PLL2 Block Diagram
Copyright © 2005–2012, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications 147
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Texas Instruments TMS320C6455 Specifications

General

Brand	Texas Instruments
Model	TMS320C6455
Category	Signal Processors
Language	English