CLKIN1
PCLK
RESET
RESETSTAT
SYSREFCLK (PLL1C)
Z Group
POR
SYSCLK3
SYSCLK4
SYSCLK5
AECLKOUT (Internal)
Boot and Device
Configuration Pins
Low Group
High Group
CLKIN2
Internal Reset PLL2C
SYSREFCLK (PLL2C)
SYSCLK1 (PLL2C)
SYSCLK2
5
9
7
8
Undefined
Undefined
Low
High-Z
Undefined
High
PLL2 Unlocked
PLL2 Locked
(A)
PLL2 Unlocked
Clock Valid
Undefined
Undefined
Undefined
Clock Valid
(B)
Power Supplies Ramping Power Supplies Stable
TMS320C6455
SPRS276M –MAY 2005–REVISED MARCH 2012
www.ti.com
A. SYSREFCLK of the PLL2 controller runs at CLKIN2 ×10.
B. SYSCLK1 of PLL2 controller runs at SYSREFCLK/2 (default).
C. Power supplies, CLKIN1, CLKIN2 (if used), and PCLK (if used) must be stable before the start of t
w(POR)
.
D. Do not tie the RESET and POR pins together.
E. The RESET pin can be brought high after the POR pin has been brought high. In this case, the RESET pin must be
held low for a minimum of t
w(RESET)
after the POR pin has been brought high.
Figure 7-8. Power-Up Timing
130 C64x+ Peripheral Information and Electrical Specifications Copyright © 2005–2012, Texas Instruments Incorporated
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