Texas Instruments TMS320C6455 User Manual

TMS320C6455
SPRS276M –MAY 2005–REVISED MARCH 2012 www.ti.com
7.14.1 EMAC Device-Specific Information
Interface Modes
The EMAC module on the TMS320C6455 device supports four interface modes: Media Independent
Interface (MII), Reduced Media Independent Interface (RMII), Gigabit Media Independent Interface (GMII),
and Reduced Gigabit Media Independent Interface (RGMII). The MII and GMII interface modes are
defined in the IEEE 802.3-2002 standard.
The RGMII mode of the EMAC conforms to the Reduced Gigabit Media Independent Interface (RGMII)
Specification (version 2.0). The RGMII mode implements the same functionality as the GMII mode, but
with a reduced number of pins. Data and control information is transmitted and received using both edges
of the transmit and receive clocks (TXC and RXC).
Note: The EMAC internally delays the transmit clock (TXC) with respect to the transmit data and control
pins. Therefore, the EMAC conforms to the RGMII-ID operation of the RGMII specification. However, the
EMAC does not delay the receive clock (RXC); this signal must be delayed with respect to the receive
data and control pins outside of the DSP.
The RMII mode of the EMAC conforms to the RMII Specification (revision 1.2), as written by the RMII
Consortium. As the name implies, the Reduced Media Independent Interface (RMII) mode is a reduced
pin count version of the MII mode.
Interface Mode Select
The EMAC uses the same pins for the MII, GMII, and RMII modes. Standalone pins are included for the
RGMII mode due to specific voltage requirements. Only one mode can be used at a time. The mode used
is selected at device reset based on the MACSEL[1:0] configuration pins (for more detailed information,
see Section 3, Device Configuration). Table 7-70 shows which multiplexed pins are used in the MII, GMII,
and RMII modes on the EMAC. For a detailed description of these pin functions, see Table 2-3, Terminal
Functions.
200 C64x+ Peripheral Information and Electrical Specifications Copyright © 2005–2012, Texas Instruments Incorporated
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Texas Instruments TMS320C6455 Specifications

General

Clock Speed	1.0 GHz
Core Count	1
On-Chip RAM	Yes
Data Width	32-bit
Data Bus Width	64-bit
Operating Voltage	1.2 V
I/O Voltage	3.3 V
Instruction Set	TMS320C64x+
Memory	DDR2
Package Type	BGA
External Memory Interface	EMIF
Interfaces	I2C, SPI

Summary

1 Features

2 Device Overview

2.1 Device Characteristics

2.2 CPU (DSP Core) Description

Details the C64x+ CPU core, functional units, register files, and data paths.

2.3 Memory Map Summary

2.4 Boot Sequence

Explains the process of initializing the DSP's memory and registers at reset.

3 Device Configuration

3.1 Device Configuration at Device Reset

Details configuration pins (AEA, ABA, PCI_EN) for boot mode, clock source, and endianness.

3.2 Peripheral Configuration at Device Reset

3.4 Device State Control Registers

3.5 Device Status Register Description

5 C64x+ Megamodule

5.1 Memory Architecture

Describes the L2, L1P, and L1D memory configurations and sizes.

5.2 Memory Protection

5.3 Bandwidth Management

6 Device Operating Conditions

6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)

Specifies stress ratings for voltage, temperature, and other conditions beyond which damage may occur.

6.2 Recommended Operating Conditions

Lists recommended operating ranges for supply voltages, input/output, and temperatures.

6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)

Details electrical characteristics under specified operating conditions.

7 C64x+ Peripheral Information and Electrical Specifications

7.1 Parameter Information

7.3 Power Supplies

Covers power supply sequencing, decoupling, and power-down operation.

7.4 Enhanced Direct Memory Access (EDMA3) Controller

Details EDMA3 features like transfer dimensions, PaRAM entries, and DMA channels.

7.5 Interrupts

7.6 Reset Controller

Describes different reset types (POR, Warm, Max, System, CPU) and their effects.

7.7 PLL1 and PLL1 Controller

Details PLL1 controller operation, clocks, and registers for frequency synthesis.

7.8 PLL2 and PLL2 Controller

Describes PLL2 controller operation, clocks, and registers for EMAC and DDR2 memory.

7.9 DDR2 Memory Controller

Explains DDR2 interface, device-specific information, and memory topologies.

7.10 External Memory Interface A (EMIFA)

Covers EMIFA interface capabilities for various external devices and timing.

7.11 I2C Peripheral

Describes the I2C module, its features, and device-specific information.

7.12 Host-Port Interface (HPI) Peripheral

7.13 Multichannel Buffered Serial Port (McBSP)

7.14 Ethernet MAC (EMAC)

Describes EMAC module, interface modes (MII, RMII, GMII, RGMII), and control modules.

7.15 Timers

7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2)

7.17 Enhanced Turbo Decoder Coprocessor (TCP2)

7.18 Peripheral Component Interconnect (PCI)

7.20 Serial RapidIO (SRIO) Port

7.22 Emulation Features and Capability