TMS320C6455
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SPRS276M –MAY 2005–REVISED MARCH 2012
Table 7-112. RapidIO Control Registers (continued)
HEX ADDRESS RANGE ACRONYM REGISTER NAME
02D0 0710 RIO_TX_CPPI_FLOW_MASKS3 Transmit CPPI Supported Flow Mask Register 3
02D0 0714 RIO_TX_CPPI_FLOW_MASKS4 Transmit CPPI Supported Flow Mask Register 4
02D0 0718 RIO_TX_CPPI_FLOW_MASKS5 Transmit CPPI Supported Flow Mask Register 5
02D0 071C RIO_TX_CPPI_FLOW_MASKS6 Transmit CPPI Supported Flow Mask Register 6
02D0 0720 RIO_TX_CPPI_FLOW_MASKS7 Transmit CPPI Supported Flow Mask Register 7
02D0 0724 - 02D0 073C - Reserved
02D0 0740 RIO_RX_QUEUE_TEAR_DOWN Receive Queue Teardown Register
02D0 0744 RIO_RX_CPPI_CNTL Receive CPPI Control Register
02D0 0748 - 02D0 07DC - Reserved
02D0 07E0 RIO_TX_QUEUE_CNTL0 Transmit CPPI Weighted Round Robin Control Register 0
02D0 07E4 RIO_TX_QUEUE_CNTL1 Transmit CPPI Weighted Round Robin Control Register 1
02D0 07E8 RIO_TX_QUEUE_CNTL2 Transmit CPPI Weighted Round Robin Control Register 2
02D0 07EC RIO_TX_QUEUE_CNTL3 Transmit CPPI Weighted Round Robin Control Register 3
02D0 07F0 - 02D0 07FC - Reserved
02D0 0800 RIO_RXU_MAP_L0 Mailbox-to-Queue Mapping Register L0
02D0 0804 RIO_RXU_MAP_H0 Mailbox-to-Queue Mapping Register H0
02D0 0808 RIO_RXU_MAP_L1 Mailbox-to-Queue Mapping Register L1
02D0 080C RIO_RXU_MAP_H1 Mailbox-to-Queue Mapping Register H1
02D0 0810 RIO_RXU_MAP_L2 Mailbox-to-Queue Mapping Register L2
02D0 0814 RIO_RXU_MAP_H2 Mailbox-to-Queue Mapping Register H2
02D0 0818 RIO_RXU_MAP_L3 Mailbox-to-Queue Mapping Register L3
02D0 081C RIO_RXU_MAP_H3 Mailbox-to-Queue Mapping Register H3
02D0 0820 RIO_RXU_MAP_L4 Mailbox-to-Queue Mapping Register L4
02D0 0824 RIO_RXU_MAP_H4 Mailbox-to-Queue Mapping Register H4
02D0 0828 RIO_RXU_MAP_L5 Mailbox-to-Queue Mapping Register L5
02D0 082C RIO_RXU_MAP_H5 Mailbox-to-Queue Mapping Register H5
02D0 0830 RIO_RXU_MAP_L6 Mailbox-to-Queue Mapping Register L6
02D0 0834 RIO_RXU_MAP_H6 Mailbox-to-Queue Mapping Register H6
02D0 0838 RIO_RXU_MAP_L7 Mailbox-to-Queue Mapping Register L7
02D0 083C RIO_RXU_MAP_H7 Mailbox-to-Queue Mapping Register H7
02D0 0840 RIO_RXU_MAP_L8 Mailbox-to-Queue Mapping Register L8
02D0 0844 RIO_RXU_MAP_H8 Mailbox-to-Queue Mapping Register H8
02D0 0848 RIO_RXU_MAP_L9 Mailbox-to-Queue Mapping Register L9
02D0 084C RIO_RXU_MAP_H9 Mailbox-to-Queue Mapping Register H9
02D0 0850 RIO_RXU_MAP_L10 Mailbox-to-Queue Mapping Register L10
02D0 0854 RIO_RXU_MAP_H10 Mailbox-to-Queue Mapping Register H10
02D0 0858 RIO_RXU_MAP_L11 Mailbox-to-Queue Mapping Register L11
02D0 085C RIO_RXU_MAP_H11 Mailbox-to-Queue Mapping Register H11
02D0 0860 RIO_RXU_MAP_L12 Mailbox-to-Queue Mapping Register L12
02D0 0864 RIO_RXU_MAP_H12 Mailbox-to-Queue Mapping Register H12
02D0 0868 RIO_RXU_MAP_L13 Mailbox-to-Queue Mapping Register L13
02D0 086C RIO_RXU_MAP_H13 Mailbox-to-Queue Mapping Register H13
02D0 0870 RIO_RXU_MAP_L14 Mailbox-to-Queue Mapping Register L14
02D0 0874 RIO_RXU_MAP_H14 Mailbox-to-Queue Mapping Register H14
02D0 0878 RIO_RXU_MAP_L15 Mailbox-to-Queue Mapping Register L15
02D0 087C RIO_RXU_MAP_H15 Mailbox-to-Queue Mapping Register H15
02D0 0880 RIO_RXU_MAP_L16 Mailbox-to-Queue Mapping Register L16
Copyright © 2005–2012, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications 239
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