TMS320C6455
SPRS276M –MAY 2005–REVISED MARCH 2012
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7.10.5 BUSREQ Timing
Table 7-50. Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles
for EMIFA Module
(see Figure 7-40)
-720
-850
A-1000/-1000
NO. PARAMETER UNIT
-1200
MIN MAX
1 t
d(AEKOH-ABUSRV)
Delay time, AECLKOUT high to ABUSREQ valid 1 5.5 ns
Figure 7-40. BUSREQ Timing for EMIFA
168 C64x+ Peripheral Information and Electrical Specifications Copyright © 2005–2012, Texas Instruments Incorporated
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