TMS320C6455
SPRS276M –MAY 2005–REVISED MARCH 2012
www.ti.com
Table 7-96. VCP2 Registers (continued)
EDMA BUS CONFIGURATION BUS
ACRONYM REGISTER NAME
HEX ADDRESS RANGE HEX ADDRESS RANGE
5800 1000 - BM Branch Metrics
5800 2000 - SM State Metric
5800 3000 - TBHD Traceback Hard Decision
5800 6000 - TBSD Traceback Soft Decision
5800 F000 - IO Decoded Bits
7.17 Enhanced Turbo Decoder Coprocessor (TCP2)
7.17.1 TCP2 Device-Specific Information
The C6455 device has a high-performance embedded coprocessor [Turbo-Decoder Coprocessor (TCP2)
that significantly speeds up channel-decoding operations on-chip. With the CPU operating at 1 GHz, the
TCP2 can decode up to forty 384-Kbps or eight 2-Mbps turbo-encoded channels (assuming 8 iterations).
The TCP2 implements the max*log-map algorithm and is designed to support all polynomials and rates
required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame
length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria
are also programmable. Communications between the TCP2 and the CPU are carried out through the
EDMA3 controller.
The TCP2 supports:
• Parallel concatenated convolutional turbo decoding using the MAP algorithm
• All turbo code rates greater than or equal to 1/5
• 3GPP and CDMA2000 turbo encoder trellis
• 3GPP and CDMA2000 block sizes in standalone mode
• Larger block sizes in shared processing mode
• Both max log MAP and log MAP decoding
• Sliding windows algorithm with variable reliability and prolog lengths
• The prolog reduction algorithm
• Execution of a minimum and maximum number of iterations
• The SNR stopping criteria algorithm
• The CRC stopping criteria algorithm
For more detailed information on the TCP2, see the TMS320C645x DSP Turbo-Decoder Coprocessor 2
(TCP2) Reference Guide (literature number SPRU973).
220 C64x+ Peripheral Information and Electrical Specifications Copyright © 2005–2012, Texas Instruments Incorporated
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