2
1
CLKS
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
TMS320C6455
www.ti.com
SPRS276M –MAY 2005–REVISED MARCH 2012
Table 7-61. Timing Requirements for FSR When GSYNC = 1
(see Figure 7-53)
-720
-850
A-1000/-1000
NO. UNIT
-1200
MIN MAX
1 t
su(FRH-CKSH)
Setup time, FSR high before CLKS high 4 ns
2 t
h(CKSH-FRH)
Hold time, FSR high after CLKS high 4 ns
Figure 7-53. FSR Timing When GSYNC = 1
Table 7-62. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
(1) (2)
(see Figure 7-54)
-720
-850
A-1000/-1000
NO. UNIT
-1200
MASTER SLAVE
MIN MAX MIN MAX
4 t
su(DRV-CKXL)
Setup time, DR valid before CLKX low 12 2 - 18P ns
5 t
h(CKXL-DRV)
Hold time, DR valid after CLKX low 4 5 + 36P ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
Copyright © 2005–2012, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications 191
Submit Documentation Feedback
Product Folder Link(s): TMS320C6455
To Next Page
Loading...
Need help?
General
