RGTXC
(at DSP)
(A)
RGTXD[3:0]
(B)
RGTXCTL
(B)
5
1st Half-byte
TXERRTXEN
2nd Half-byte
1
Internal RGTXC
RGTXC at DSP pins
4
4
2
3
1
2
6
TMS320C6455
SPRS276M –MAY 2005–REVISED MARCH 2012
www.ti.com
Table 7-88. Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII
Transmit
(1)
(see Figure 7-70)
-720
-850
A-1000/-1000
NO. PARAMETER UNIT
-1200
MIN MAX
Setup time, transmit selected signals valid before RGTXC (at DSP)
5 t
su(RGTXD-RGTXCH)
1.2 ns
high/low
6 t
h(RGTXCH-RGTXD)
Hold time, transmit selected signals valid after RGTXC (at DSP) high/low 1.2
(1) For RGMII, transmit selected signals include: RGTXD[3:0] and RGTXCTL.
A. RGTXC is delayed internally before being driven to the RGTXC pin.
B. Data and control information is transmitted using both edges of the clocks. RGTXD[3:0] carries data bits 3-0 on the
rising edge of RGTXC and data bits 7-4 on the falling edge of RGTXC. Similarly, RGTXCTL carries TXEN on rising
edge of RGTXC and TXERR of falling edge.
Figure 7-70. EMAC Transmit Interface Timing [RGMII Operation]
214 C64x+ Peripheral Information and Electrical Specifications Copyright © 2005–2012, Texas Instruments Incorporated
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