TMS320C6455
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SPRS276M –MAY 2005–REVISED MARCH 2012
Table 7-112. RapidIO Control Registers (continued)
HEX ADDRESS RANGE ACRONYM REGISTER NAME
02D0 042C RIO_LSU2_REG3 LSU2 Control Register 3
02D0 0430 RIO_LSU2_REG4 LSU2 Control Register 4
02D0 0434 RIO_LSU2_REG5 LSU2 Control Register 5
02D0 0438 RIO_LSU2_REG6 LSU2 Control Register 6
02D0 043C RIO_LSU2_FLOW_MASKS1 LSU2 Congestion Control Flow Mask Register
02D0 0440 RIO_LSU3_REG0 LSU3 Control Register 0
02D0 0444 RIO_LSU3_REG1 LSU3 Control Register 1
02D0 0448 RIO_LSU3_REG2 LSU3 Control Register 2
02D0 044C RIO_LSU3_REG3 LSU3 Control Register 3
02D0 0450 RIO_LSU3_REG4 LSU3 Control Register 4
02D0 0454 RIO_LSU3_REG5 LSU3 Control Register 5
02D0 0458 RIO_LSU3_REG6 LSU3 Control Register 6
02D0 045C RIO_LSU3_FLOW_MASKS2 LSU3 Congestion Control Flow Mask Register
02D0 0460 RIO_LSU4_REG0 LSU4 Control Register 0
02D0 0464 RIO_LSU4_REG1 LSU4 Control Register 1
02D0 0468 RIO_LSU4_REG2 LSU4 Control Register 2
02D0 046C RIO_LSU4_REG3 LSU4 Control Register 3
02D0 0470 RIO_LSU4_REG4 LSU4 Control Register 4
02D0 0474 RIO_LSU4_REG5 LSU4 Control Register 5
02D0 0478 RIO_LSU4_REG6 LSU4 Control Register 6
02D0 047C RIO_LSU4_FLOW_MASKS3 LSU4 Congestion Control Flow Mask Register
02D0 0480 - 02D0 04FC - Reserved
02D0 0500 RIO_QUEUE0_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 0
02D0 0504 RIO_QUEUE1_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 1
02D0 0508 RIO_QUEUE2_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 2
02D0 050C RIO_QUEUE3_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 3
02D0 0510 RIO_QUEUE4_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 4
02D0 0514 RIO_QUEUE5_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 5
02D0 0518 RIO_QUEUE6_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 6
02D0 051C RIO_QUEUE7_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 7
02D0 0520 RIO_QUEUE8_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 8
02D0 0524 RIO_QUEUE9_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 9
02D0 0528 RIO_QUEUE10_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 10
02D0 052C RIO_QUEUE11_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 11
02D0 0530 RIO_QUEUE12_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 12
02D0 0534 RIO_QUEUE13_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 13
02D0 0538 RIO_QUEUE14_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 14
02D0 053C RIO_QUEUE15_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 15
02D0 0540 - 02D0 057C - Reserved
02D0 0580 RIO_QUEUE0_TXDMA_CP Queue Transmit DMA Completion Pointer Register 0
02D0 0584 RIO_QUEUE1_TXDMA_CP Queue Transmit DMA Completion Pointer Register 1
02D0 0588 RIO_QUEUE2_TXDMA_CP Queue Transmit DMA Completion Pointer Register 2
02D0 058C RIO_QUEUE3_TXDMA_CP Queue Transmit DMA Completion Pointer Register 3
02D0 0590 RIO_QUEUE4_TXDMA_CP Queue Transmit DMA Completion Pointer Register 4
02D0 0594 RIO_QUEUE5_TXDMA_CP Queue Transmit DMA Completion Pointer Register 5
02D0 0598 RIO_QUEUE6_TXDMA_CP Queue Transmit DMA Completion Pointer Register 6
02D0 059C RIO_QUEUE7_TXDMA_CP Queue Transmit DMA Completion Pointer Register 7
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