Texas Instruments TMS320C6455 User Manual

TMS320C6455
www.ti.com SPRS276M –MAY 2005–REVISED MARCH 2012
Table 7-70. EMAC/MDIO Multiplexed Pins (MII, RMII, and GMII Modes)
BALL NUMBER DEVICE PIN NAME MII RMII GMII
(MAC_SEL = (MAC_SEL = (MAC_SEL =
00b) 01b) 10b)
J2 URDATA0/MRXD0/RMRXD0 MRXD0 RMRXD0 MRXD0
H3 URDATA1/MRXD1/RMRXD1 MRXD1 RMRXD1 MRXD1
J1 URDATA2/MRXD2 MRXD2 MRXD2
J3 URDATA3/MRXD3 MRXD3 MRXD3
L1 URDATA4/MRXD4 MRXD4
L2 URDATA5/MRXD5 MRXD5
H2 URDATA6/MRXD6 MRXD6
M2 URDATA7/MRXD7 MRXD7
M1 UXDATA0/MTXD0/RMTXD0 MTXD0 RMTXD0 MTXD0
L4 UXDATA1/MTXD1/RMTXD1 MTXD1 RMTXD1 MTXD1
M4 UXDATA2/MTXD2 MTXD2 MTXD2
K4 UXDATA3/MTXD3 MTXD3 MTXD3
L3 UXDATA4/MTXD4 MTXD4
L5 UXDATA5/MTXD5 MTXD5
M3 UXDATA6/MTXD6 MTXD6
N5 UXDATA7/MTXD7 MTXD7
H4 URSOC/MRXER/RMRXER MRXER RMRXER MRXER
H5 URENB/MRXDV MRXDV MRXDV
J5 UXENB/MTXEN/RMTXEN MTXEN RMTXEN MTXEN
J4 URCLAV/MCRS/RMCRSDV MCRS RMCRSDV MCRS
K3 UXSOC/MCOL MCOL MCOL
K5 UXCLAV/GMTCLK GMTCLK
H1 URCLK/MRCLK MRCLK MRCLK
N4 UXCLK/MTCLK/REFCLK MTCLK RMREFCLK MTCLK
N3 UXADDR3/GMDIO MDIO MDIO MDIO
M5 UXADDR4/GMDCLK MDCLK MDCLK MDCLK
Using the RMII Mode of the EMAC
The Ethernet Media Access Controller (EMAC) contains logic that allows it to communicate using the
Reduced Media Independent Interface (RMII) protocol. This logic must be taken out of reset before being
used. To use the RMII mode of the EMAC follow these steps:
1. Enable the EMAC/MDIO through the Device State Control Registers.
– Unlock the PERCFG0 register by writing 0x0F0A 0B00 to the PERLOCK register.
– Set bit 4 in the PERCFG0 register within 16 SYSCLK3 clock cycles to enable the EMAC/MDIO.
– Poll the PERSTAT0 register to verify state change.
2. Initialize the EMAC/MDIO as needed.
3. Release the RMII logic from reset by clearing the RMII_RST bit of the EMAC Configuration Register
(see Section 3.4.5).
As described in the previous section, the RMII mode of the EMAC must be selected by setting
MACSEL[1:0] = 01b at device reset.
Copyright © 2005–2012, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications 201
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Texas Instruments TMS320C6455 Specifications

General

Clock Speed	1.0 GHz
Core Count	1
On-Chip RAM	Yes
Data Width	32-bit
Data Bus Width	64-bit
Operating Voltage	1.2 V
I/O Voltage	3.3 V
Instruction Set	TMS320C64x+
Memory	DDR2
Package Type	BGA
External Memory Interface	EMIF
Interfaces	I2C, SPI

Summary

1 Features

2 Device Overview

2.1 Device Characteristics

2.2 CPU (DSP Core) Description

Details the C64x+ CPU core, functional units, register files, and data paths.

2.3 Memory Map Summary

2.4 Boot Sequence

Explains the process of initializing the DSP's memory and registers at reset.

3 Device Configuration

3.1 Device Configuration at Device Reset

Details configuration pins (AEA, ABA, PCI_EN) for boot mode, clock source, and endianness.

3.2 Peripheral Configuration at Device Reset

3.4 Device State Control Registers

3.5 Device Status Register Description

5 C64x+ Megamodule

5.1 Memory Architecture

Describes the L2, L1P, and L1D memory configurations and sizes.

5.2 Memory Protection

5.3 Bandwidth Management

6 Device Operating Conditions

6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)

Specifies stress ratings for voltage, temperature, and other conditions beyond which damage may occur.

6.2 Recommended Operating Conditions

Lists recommended operating ranges for supply voltages, input/output, and temperatures.

6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)

Details electrical characteristics under specified operating conditions.

7 C64x+ Peripheral Information and Electrical Specifications

7.1 Parameter Information

7.3 Power Supplies

Covers power supply sequencing, decoupling, and power-down operation.

7.4 Enhanced Direct Memory Access (EDMA3) Controller

Details EDMA3 features like transfer dimensions, PaRAM entries, and DMA channels.

7.5 Interrupts

7.6 Reset Controller

Describes different reset types (POR, Warm, Max, System, CPU) and their effects.

7.7 PLL1 and PLL1 Controller

Details PLL1 controller operation, clocks, and registers for frequency synthesis.

7.8 PLL2 and PLL2 Controller

Describes PLL2 controller operation, clocks, and registers for EMAC and DDR2 memory.

7.9 DDR2 Memory Controller

Explains DDR2 interface, device-specific information, and memory topologies.

7.10 External Memory Interface A (EMIFA)

Covers EMIFA interface capabilities for various external devices and timing.

7.11 I2C Peripheral

Describes the I2C module, its features, and device-specific information.

7.12 Host-Port Interface (HPI) Peripheral

7.13 Multichannel Buffered Serial Port (McBSP)

7.14 Ethernet MAC (EMAC)

Describes EMAC module, interface modes (MII, RMII, GMII, RGMII), and control modules.

7.15 Timers

7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2)

7.17 Enhanced Turbo Decoder Coprocessor (TCP2)

7.18 Peripheral Component Interconnect (PCI)

7.20 Serial RapidIO (SRIO) Port

7.22 Emulation Features and Capability