TMS320C6455
SPRS276M –MAY 2005–REVISED MARCH 2012
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4.2 Data Switch Fabric Connections
Figure 4-1 shows the connection between slaves and masters through the data switched central resource
(SCR). Masters are shown on the right and slaves on the left. The data SCR connects masters to slaves
via 128-bit data buses running at a SYSCLK2 frequency. SYSCLK2 is supplied by the PLL1 controller and
is fixed at a frequency equal to the CPU frequency divided by 3.
Some peripherals, like PCI and the C64x+ Megamodule, have both slave and master ports. Note that
each EDMA3 transfer controller has an independent connection to the data SCR.
The Serial RapidIO (SRIO) peripheral has two connections to the data SCR. The first connection is used
when descriptors are being fetched from system memory. The other connection is used for all other data
transfers.
Note that masters can access the configuration SCR through the data SCR. The configuration SCR is
described in Section 4.3.
Not all masters on the C6455 DSP may connect to all slaves. Allowed connections are summarized in
Table 4-1 .
78 System Interconnect Copyright © 2005–2012, Texas Instruments Incorporated
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