HCS
HAS
HR/W
HHWIL
HSTROBE
(A)
HD[15:0]
HRDY
(B)
2
3
1
37
9
10
14
2
38
12
11
12
11
12
11
13
7
6
1
3
13
37
9
10
36
HCNTL[1:0]
12
11
12
11
12
11
TMS320C6455
SPRS276M –MAY 2005–REVISED MARCH 2012
www.ti.com
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-
incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed information on
the HPI peripheral, see the TMS320C645x DSP Host Port Interface (HPI) User's Guide (literature number
SPRU969) .
Figure 7-45. HPI16 Read Timing (HAS Used)
178 C64x+ Peripheral Information and Electrical Specifications Copyright © 2005–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TMS320C6455
To Next Page
Loading...
Need help?
General
