TMS320C6455
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SPRS276M –MAY 2005–REVISED MARCH 2012
Table 3-1. C6455 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued)
CONFIGURATION IPD/
NO. FUNCTIONAL DESCRIPTION
PIN IPU
(1)
SYSCLKOUT Enable bit (SYSCLKOUT_EN).
Selects which function is enabled on the SYSCLK4/GP[1] muxed pin.
AEA4 T28 IPD
0 GP[1] pin function is enabled (default)
1 SYSCLK4 pin function is enabled
For proper C6455 device operation, the AEA3 pin must be pulled up at device reset using a
1-kΩ resistor if power is applied to the SRIO supply pins. If the SRIO peripheral is not used
AEA3 T27 IPD
and the SRIO supply pins are connected to V
SS
, the AEA3 pin must be pulled down to V
SS
using a 1-kΩ resistor.
Configuration General-Purpose Inputs (CFGGP[2:0])
[T26,
The value of these pins is latched to the Device Status Register following device reset and is
AEA[2:0] U26, IPD
used by the on-chip bootloader for some boot modes. For more information on the boot
U25]
modes, see Section 2.4, Boot Sequence.
PCI pin function enable bit (PCI_EN).
Selects which function is enabled on the HPI/PCI and the PCI/UTOPIA multiplexed pins.
0 HPI and UTOPIA pin function enabled (default)
PCI_EN Y29 IPD This means all multiplexed HPI/PCI and PCI/UTOPIA pins function as HPI and
UTOPIA pins, respectively .
1 PCI pin function enabled
This means all multiplexed HPI/PCI and PCI/UTOPIA pins function as PCI pins.
DDR2 Memory Controller enable (DDR2_EN).
ABA0 V26 IPD 0 DDR2 Memory Controller peripheral pins are disabled (default)
1 DDR2 Memory Controller peripheral pins are enabled
EMIFA enable (EMIFA_EN).
ABA1 V25 IPD 0 EMIFA peripheral pins are disabled (default)
1 EMIFA peripheral pins are enabled
3.2 Peripheral Configuration at Device Reset
Some C6455 device peripherals share the same pins (internally multiplexed) and are mutually exclusive.
Therefore, not all peripherals may be used at the same time. The device configuration pins described in
Section 3.1, Device Configuration at Device Reset, determine which function is enabled for the multiplexed
pins.
Note that when the pin function of a peripheral is disabled at device reset, the peripheral is permanently
disabled and cannot be enabled until its pin function is enabled and another device reset is executed.
Also, note that enabling the pin function of a peripheral does not enable the corresponding peripheral. All
peripherals on the C6455 device are disabled by default, except when used for boot, and must be enabled
through software before being used.
Other peripheral options like PCI clock speed and EMAC/MDIO interface mode can also be selected at
device reset through the device configuration pins. The configuration selected is also fixed at device reset
and cannot be changed until another device reset is executed with a different configuration selected.
The multiply factor of the PLL1 Controller is not selected through the configuration pins. The PLL1 multiply
factor is set in software through the PLL1 controller registers after device reset. The PLL2 multiply factor is
fixed. For more information, see Section 7.7, PLL1 and PLL1 Controller, and Section 7.8, PLL2 and PLL2
Controller.
On the C6455 device, the PCI peripheral pins are multiplexed with the HPI pins and partially multiplexed
with the UTOPIA pins. The PCI_EN pin selects the function for the HPI/PCI multiplexed pins. The PCI66,
PCI_EEAI, and HPI_WIDTH control other functions of the PCI and HPI peripherals. Table 3-2 describes
the effect of the PCI_EN, PCI66, PCI_EEAI, and HPI_WIDTH configuration pins.
Copyright © 2005–2012, Texas Instruments Incorporated Device Configuration 57
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