Texas Instruments TMS320C6455 User Manual

TMS320C6455
www.ti.com SPRS276M –MAY 2005–REVISED MARCH 2012
Table 7-60. Switching Characteristics Over Recommended Operating Conditions for McBSP
(1) (2)
(see Figure 7-52)
-720
-850
A-1000/-1000
NO. PARAMETER UNIT
-1200
MIN MAX
Delay time, CLKS high to CLKR/X high for internal CLKR/X
1 t
d(CKSH-CKRXH)
1.4 10 ns
generated from CLKS input
(3)
2 t
c(CKRX)
Cycle time, CLKR/X CLKR/X int 6P or 10
(4) (5) (6)
ns
3 t
w(CKRX)
Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C - 1
(7)
C + 1
(7)
ns
4 t
d(CKRH-FRV)
Delay time, CLKR high to internal FSR valid CLKR int -2.1 3.3 ns
CLKX int -1.7 3
9 t
d(CKXH-FXV)
Delay time, CLKX high to internal FSX valid ns
CLKX ext 1.7 9
CLKX int -3.9 4
Disable time, DX high impedance following
12 t
dis(CKXH-DXHZ)
ns
last data bit from CLKX high
CLKX ext 2.1 9
CLKX int -3.9 + D1
(8)
4 + D2
(8)
13 t
d(CKXH-DXV)
Delay time, CLKX high to DX valid ns
CLKX ext 2.1 + D1
(8)
9 + D2
(8)
Delay time, FSX high to DX valid FSX int -2.3 + D1
(9)
5.6 + D2
(9)
14 t
d(FXH-DXV)
ns
ONLY applies when in data
FSX ext 1.9 + D1
(9)
9 + D2
(9)
delay 0 (XDATDLY = 00b) mode
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) The CLKS signal is shared by both McBSP0 and McBSP1 on this device.
(4) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
(5) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(6) Use whichever value is greater.
(7) C = H or L
S = sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
(8) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(9) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
Copyright © 2005–2012, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications 189
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Texas Instruments TMS320C6455 Specifications

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Brand	Texas Instruments
Model	TMS320C6455
Category	Signal Processors
Language	English