Texas Instruments TMS320C6455 User Manual

P48 H1 H2 H3
N 0x1F N+1 0x1F N+2 0x1F
N N+1 N+2
1211
9
10
5
4
3
2
1
URCLK
URDATA[7:0]
URADDR[4:0]
URCLAV
URENB
URSOC
A. The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the URCLAV and
URSOC signals).
8
6
7
TMS320C6455
SPRS276M –MAY 2005–REVISED MARCH 2012 www.ti.com
Table 7-110. Timing Requirements for UTOPIA Slave Receive
(see Figure 7-77)
-720
-850
A-1000/-1000
NO. UNIT
-1200
MIN MAX
1 t
su(URDV-URCH)
Setup time, URDATA valid before URCLK high 4 ns
2 t
h(URCH-URDV)
Hold time, URADDR valid after URCLK high 1 ns
3 t
su(URAV-URCH)
Setup time, URADDR valid before URCLK high 4 ns
4 t
h(URCH-URAV)
Hold time, URADDR valid after URCLK high 1 ns
9 t
su(URENBL-URCH)
Setup time, URENB low before URCLK high 4 ns
10 t
h(URCH-URENBL)
Hold time, URENB low after URCLK high 1 ns
11 t
su(URSH-URCH)
Setup time, URSOC high before URCLK high 4 ns
12 t
h(URCH-URSH)
Hold time, URSOC high after URCLK high 1 ns
Table 7-111. Switching Characteristics Over Recommended Operating Conditions for UTOPIA Slave
Receive Cycles
(see Figure 7-77)
-720
-850
A-1000/-1000
NO. PARAMETER UNIT
-1200
MIN MAX
5 t
d(URCH-URCLAV)
Delay time, URCLK high to URCLAV driven active value 3 12 ns
6 t
d(URCH-URCLAVL)
Delay time, URCLK high to URCLAV driven inactive low 3 12 ns
7 t
d(URCH-URCLAVHZ)
Delay time, URCLK high to URCLAV going Hi-Z 9 18.5 ns
8 t
w(URCLAVL-URCLAVHZ)
Pulse duration (low), URCLAV low to URCLAV Hi-Z 3 ns
Figure 7-77. UTOPIA Slave Receive Timing
(A)
232 C64x+ Peripheral Information and Electrical Specifications Copyright © 2005–2012, Texas Instruments Incorporated
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Texas Instruments TMS320C6455 Specifications

General

Brand	Texas Instruments
Model	TMS320C6455
Category	Signal Processors
Language	English