Texas Instruments TMS320C6455 User Manual

TMS320C6455
SPRS276M –MAY 2005–REVISED MARCH 2012 www.ti.com
Table 2-3. Terminal Functions (continued)
SIGNAL
TYPE
(1)
IPD/IPU
(2)
DESCRIPTION
NAME NO.
URADDR2/PINTA
(6)
/ UTOPIA received address pin 2 (URADDR2) (I) or PCI interrupt A (O/Z) or
P3 I/O/Z
GP[14] GP[14] (I/O/Z) default]
URADDR1/PRST/ UTOPIA received address pin 1 (URADDR1) (I) or PCI reset (I) or GP[13]
R5 I/O/Z
GP[13] (I/O/Z) [default]
URADDR0/PGNT/ UTOPIA received address pin 0 (URADDR0) (I) or PCI bus grant (I) or GP[12]
R4 I/O/Z
GP[12] (I/O/Z)[default]
URADDR4/PCBE0/ UTOPIA received address pin 4 (URADDR4) (I) or PCI command/byte enable 0
P1 I/O/Z
GP[2] (I/O/Z) or GP[2] (I/O/Z)[default]
UTOPIA transmit address pin 2 (UXADDR2) (I) or PCI command/byte enable 3
UXADDR2/PCBE3 P5 I/O/Z
(I/O/Z). By default, this pin has no function.
UTOPIA transmit address pin 1 (UXADDR1) (I) or PCI initialization device
UXADDR1/PIDSEL R3 I
select (I). By default, this pin has no function.
UTOPIA transmit address pin 0 (UXADDR0) (I) or PCI target ready (PRTDY)
UXADDR0/PTRDY P4 I/O/Z
(I/O/Z). By default, this pin has no function.
HD31/AD31 AA3
HD30/AD30 AA5
HD29/AD29 AC4
HD28/AD28 AA4
HD27/AD27 AC5
HD26/AD26 Y1
HD25/AD25 AD2
HD24/AD24 W1
Host-port data [31:16] pin (I/O/Z) [default] or PCI data-address bus [31:16]
I/O/Z
(I/O/Z)
HD23/AD23 AC3
HD22/AD22 AE1
HD21/AD21 AD1
HD20/AD20 W2
HD19/AD19 AC1
HD18/AD18 Y2
HD17/AD17 AB1
HD16/AD16 Y3
HD15/AD15 AB2
HD14/AD14 W4
HD13/AD13 AC2
HD12/AD12 V4
HD11/AD11 AF3
HD10/AD10 AE3
HD9/AD9 AB3
HD8/AD8 W5
I/O/Z Host-port data [15:0] pin (I/O/Z) [default] or PCI data-address bus [15:0] (I/O/Z)
HD7/AD7 AB4
HD6/AD6 Y4
HD5/AD5 AD3
HD4/AD4 Y5
HD3/AD3 AD4
HD2/AD2 W6
HD1/AD1 AB5
HD0/AD0 AE2
28 Device Overview Copyright © 2005–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TMS320C6455

Texas Instruments TMS320C6455 Specifications

General

Brand	Texas Instruments
Model	TMS320C6455
Category	Signal Processors
Language	English