Xilinx SelectIO 7 Series User Manual

7 Series FPGAs SelectIO Resources User Guide www.xilinx.com UG471 (v1.10) May 8, 2018
05/13/2014 1.4
(Cont’d)
Added to list of criteria after Table 1-44. Added note to Table 1-48. Updated description
after Table 1-51. Updated V
CCO
Input column in Table 1-55. Added note 3 to Table 1-56.
Updated DLYIN connection in Figure 2-4. Updated Clock Input - C, page 117. Updated
description of PIPE_SEL in Table 2-5 and Table 2-14. Added VAR_LOAD description to
first paragraph of Stability after an Increment/Decrement Operation, page 123.
Removed center I/Os from Figure 2-16. Updated Data Output - DATAOUT, page 135. In
ODELAY Modes, replaced ODELAYCTRL with IDELAYCTRL.
In Table 3-1, added CLKDIVP and updated descriptions of OCLK and OCLKB. Updated
High-Speed Clock for Strobe-Based Memory Interfaces and Oversampling Mode -
OCLK and Reset Input - RST. Added IOBDELAY to Table 3-2. Updated bullets in
MEMORY Interface Type. Updated bullets in OVERSAMPLE Interface Type. Updated
Figure 3-7. Added sentence about ISERDESE2 being reset to Guidelines for Using the
Bitslip Submodule. Removed Bitslip submodule from description of CLKDIV in
Table 3-6. Added TBYTE_CTL and TBYTE_SRC to Table 3-7. In Figure 3-18, shifted OQ,
TQ, and OBUFT.O by one CLK edge.
05/15/2015 1.5 Added paragraph about overvoltage protection mode to V
CCO
. Added State of I/Os
During and After Configuration. Updated Special DCI Requirements for Some Banks.
In IOSTANDARD Attribute, replaced DIFF_HSTL18_II with DIFF_HSTL_II_18.
Reversed R
VRN
and R
VRP
resistors in left side IOB of DCI terminations in Figure 1-49,
Figure 1-50, Figure 1-52, Figure 1-54, Figure 1-57, Figure 1-58, Figure 1-60, and
Figure 1-62. Added note 2 to Table 1-55. Added Vivado Design Suite to Pin Planning to
Mitigate SSO Sensitivity.
Updated description of clock input C in IDELAY Ports and ODELAY Ports. Replaced SR
with S/R in Figure 2-17, Figure 2-20, and Table 2-10.
09/18/2015 1.6 Replaced SR with S/R throughout. Added note about set and reset pins to Table 2-1 and
Table 2-10. In RDY - Ready, updated sentence about RDY signal being deasserted if
REFCLK is held High or Low for more than one clock period.
In Table 3-6, changed TBYTEOUT port type from input to output.
09/15/2016 1.7 Updated first paragraph of V
CCO
. Added reference to UG912: Vivado Design Suite
Properties Reference Guide in Uncalibrated Split Termination in High-Range I/O Banks
(IN_TERM) and 7 Series FPGA SelectIO Attributes/Constraints. Added description of
termination for unused I/Os to PULLUP/PULLDOWN/KEEPER Attribute for IBUF,
OBUFT, and IOBUF.
Updated third bullet in OSERDESE2 Clocking Methods. In Table 3-11, updated DDR
14:1 latency to 5 CLK cycles.
09/27/2016 1.8 Added Spartan-7 family to Preface. Updated Reset Input - RST. Removed bullet
describing CLK driven by BUFG and CLKDIV driven by a different BUFG from
NETWORKING Interface Type and OSERDESE2 Clocking Methods.
08/22/2017 1.9 Replaced HR with HP in second paragraph of V
CCO
. Expanded description of ZHOLD
in ILOGIC Resources. Updated REFCLK_FREQUENCY value and description in
Table 2-5 and Table 2-14. Updated description of Clock Input from Clock Buffer -
CLKIN.
Updated descriptions of SHIFTOUT1, SHIFTOUT2, SHIFTIN1, and SHIFTIN2 in
Table 3-6. Updated input span to D1–D8 in Timing Characteristics of 8:1 DDR
Serialization.
05/08/2018 1.10 Expanded descriptions in Parallel 3-state Inputs - T1 to T4 and DATA_RATE_TQ
Attribute. Added note after Table 3-11.
Date Version Revision

Xilinx SelectIO 7 Series Specifications

General

Brand	Xilinx
Model	SelectIO 7 Series
Category	Computer Hardware
Language	English