The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-55
ID121610 Non-Confidential
3.5.10 SHADD16 and SHADD8
Signed Halving Add 16 and Signed Halving Add 8.
Syntax
op{cond}{Rd,} Rn, Rm
where:
op
Is any of:
SHADD16
Signed Halving Add 16
SHADD8
Signed Halving Add 8
cond
Is an optional condition code, see Conditional execution on page 3-18.
Rd
Specifies the destination register.
Rn
Specifies the first operand register.
Rm
Specifies the second operand register.
Operation
Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the
result to the destination register:
The
SHADD16
instruction:
1. Adds each halfword from the first operand to the corresponding halfword
of the second operand.
2. Shuffles the result by one bit to the right, halving the data.
3. Writes the halfword results in the destination register.
The
SHADDB8
instruction:
1. Adds each byte of the first operand to the corresponding byte of the second
operand.
2. Shuffles the result by one bit to the right, halving the data.
3. Writes the byte results in the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition flags
These instructions do not change the flags.
Examples
SHADD16 R1, R0 ; Adds halfwords in R0 to corresponding halfword of R1 and
; writes halved result to corresponding halfword in R1
SHADD8 R4, R0, R5 ; Adds bytes of R0 to corresponding byte in R5 and
; writes halved result to corresponding byte in R4.
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