ARM Cortex-M4 - Priority Mask Register; Fault Mask Register

The Cortex-M4 Processor
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 2-8
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Priority Mask Register
The PRIMASK register prevents activation of all exceptions with configurable priority. See the
register summary in Table 2-2 on page 2-3 for its attributes. The bit assignments are:
Fault Mask Register
The FAULTMASK register prevents activation of all exceptions except for Non-Maskable
Interrupt (NMI). See the register summary in Table 2-2 on page 2-3 for its attributes. The bit
assignments are:
The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the
NMI handler.
Table 2-7 PRIMASK register bit assignments
Bits Name Function
[31:1] - Reserved
[0] PRIMASK 0 = no effect
1 = prevents the activation of all exceptions with configurable priority.
Table 2-8 FAULTMASK register bit assignments
Bits Name Function
[31:1] - Reserved
[0] FAULTMASK 0 = no effect
1 = prevents the activation of all exceptions except for NMI.
31
Reserved
10
PRIMASK
Reserved
0
131
FAULTMASK