The Cortex-M4 Processor
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 2-18
ID121610 Non-Confidential
2.2.6 Memory endianness
The processor views memory as a linear collection of bytes numbered in ascending order from
zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored
word. The memory endianness used is implementation-defined, and the following subsections
describe the possible implementations:
• Byte-invariant big-endian format
• Little-endian format.
Read the AIRCR.ENDIANNESS field to find the implemented endianness, see Application
Interrupt and Reset Control Register on page 4-16.
Byte-invariant big-endian format
In byte-invariant big-endian format, the processor stores the most significant byte of a word at
the lowest-numbered byte, and the least significant byte at the highest-numbered byte. For
example:
Little-endian format
In little-endian format, the processor stores the least significant byte of a word at the
lowest-numbered byte, and the most significant byte at the highest-numbered byte. For
example:
2.2.7 Synchronization primitives
The Cortex-M4 instruction set includes pairs of synchronization primitives. These provide a
non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory
location. Software can use them to perform a guaranteed read-modify-write memory update
sequence, or for a semaphore mechanism.
Memory Register
Address A
A+1
msbyte
lsbyte
A+2
A+3
07
B3B2B0 B1
31 24 23 1615 8 7 0
B0
B1
B2
B3
Memory Register
Address A
A+1
lsbyte
msbyte
A+2
A+3
07
B0B1B3 B2
31 24 23 1615 8 7 0
B0
B1
B2
B3
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