ARM Cortex-M4 - Vfnma, Vfnms

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-136
ID121610 Non-Confidential
3.11.9 VFNMA, VFNMS
Floating-point Fused Negate Multiply Accumulate and Subtract.
Syntax
VFNMA{cond}.F32 {Sd,} Sn, Sm
VFNMS{cond}.F32 {Sd,} Sn, Sm
where:
cond Is an optional condition code, see Conditional execution on page 3-18.
Sd Specifies the destination register.
Sn, Sm Are the operand registers.
Operation
The
VFNMA instruction:
1. Negates the first floating-point operand register.
2. Multiplies the first floating-point operand with second floating-point operand.
3. Adds the negation of the floating -point destination register to the product
4. Places the result into the destination register.
The result of the multiply is not rounded before the addition.
The
VFNMS instruction:
1. Multiplies the first floating-point operand with second floating-point operand.
2. Adds the negation of the floating-point value in the destination register to the product.
3. Places the result in the destination register.
The result of the multiply is not rounded before the addition.
Restrictions
There are no restrictions.
Condition flags
These instructions do not change the flags.