The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-157
ID121610 Non-Confidential
3.12 Miscellaneous instructions
Table 3-16 shows the remaining Cortex-M4 instructions:
Table 3-16 Miscellaneous instructions
Mnemonic Brief description See
BKPT
Breakpoint BKPT on page 3-158
CPSID
Change Processor State, Disable Interrupts CPS on page 3-159
CPSIE
Change Processor State, Enable Interrupts CPS on page 3-159
DMB
Data Memory Barrier DMB on page 3-160
DSB
Data Synchronization Barrier DSB on page 3-161
ISB
Instruction Synchronization Barrier ISB on page 3-162
MRS
Move from special register to register MRS on page 3-163
MSR
Move from register to special register MSR on page 3-164
NOP
No Operation NOP on page 3-165
SEV
Send Event SEV on page 3-166
SVC
Supervisor Call SVC on page 3-167
WFE
Wait For Event WFE on page 3-168
WFI
Wait For Interrupt WFI on page 3-169
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