ARM Cortex-M4 - SMUL and SMULW

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-91
ID121610 Non-Confidential
3.6.10 SMUL and SMULW
Signed Multiply (halfwords) and Signed Multiply (word by halfword).
Syntax
op{XY}{cond} Rd,Rn, Rm
op{Y}{cond} Rd. Rn, Rm
For SMULXY only:
op Is one of:
SMUL{XY} Signed Multiply (halfwords)
X and Y specify which halfword of the source registers Rn and Rm is used as the first
and second multiply operand. If
X is B , then the bottom halfword, bits [15:0] of Rn
is used. If
X is T , then the top halfword, bits [31:16] of Rn is used. If Y is B , then the
bottom halfword, bits [15:0], of
Rm is used. If Y is T , then the top halfword, bits
[31:16], of
Rm is used.
SMULW{Y} Signed Multiply (word by halfword)
Y specifies which halfword of the source register
Rm is used as the second multiply
operand. If
Y is B , then the bottom halfword (bits [15:0]) of Rm is used. If Y is T ,
then the top halfword (bits [31:16]) of
Rm is used.
cond Is an optional condition code, see Conditional execution on page 3-18.
Rd Specifies the destination register.
Rn, Rm Are registers holding the first and second operands.
Operation
The
SMULBB , SMULTB , SMULBT and SMULTT instructions interprets the values from Rn and Rm as four
signed 16-bit integers. These instructions:
• Multiplies the specified signed halfword, Top or Bottom, values from
Rn and Rm .
• Writes the 32-bit result of the multiplication in
Rd.
The SMULWT and SMULWB instructions interprets the values from Rn as a 32-bit signed integer and
Rm as two halfword 16-bit signed integers. These instructions:
• Multiplies the first operand and the top, T suffix, or the bottom, B suffix, halfword of the
second operand.
• Writes the signed most significant 32 bits of the 48-bit result in the destination register.
Restrictions
In these instructions:
• Do not use SP and do not use PC.
•
RdHi and RdLo must be different registers.