The Cortex-M4 Processor
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 2-26
ID121610 Non-Confidential
Late-arriving This mechanism speeds up preemption. If a higher priority exception
occurs during state saving for a previous exception, the processor switches
to handle the higher priority exception and initiates the vector fetch for
that exception. State saving is not affected by late arrival because the state
saved is the same for both exceptions. Therefore the state saving continues
uninterrupted. The processor can accept a late arriving exception until the
first instruction of the exception handler of the original exception enters
the execute stage of the processor. On return from the exception handler
of the late-arriving exception, the normal tail-chaining rules apply.
Exception entry
Exception entry occurs when there is a pending exception with sufficient priority and either:
• the processor is in Thread mode
• the new exception is of higher priority than the exception being handled, in which case
the new exception preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask
registers, see Exception mask registers on page 2-7. An exception with less priority than this is
pending but is not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving
exception, the processor pushes information onto the current stack. This operation is referred to
as stacking and the structure of eight data words is referred as the stack frame.
When using floating-point routines the Cortex-M4 processor automatically stacks the
architected floating-point state on exception entry. Figure 2-3 on page 2-27 shows the
Cortex-M4 stack frame layout when floating-point state is preserved on the stack as the result
of an interrupt or an exception.
Where stack space for floating-point state is not allocated, the stack frame is the same as that of
ARMv7-M implementations without an FPU. Figure 2-3 on page 2-27 shows this stack frame
also.
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