ARM Cortex-M4 - Interrupt Clear-Enable Registers; Interrupt Set-Pending Registers

Cortex-M4 Peripherals
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 4-5
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4.2.3 Interrupt Clear-enable Registers
The NVIC_ICER0-NVIC_ICER7 registers disable interrupts, and show which interrupts are
enabled. See the register summary in Table 4-2 on page 4-3 for the register attributes.
The bit assignments are:
4.2.4 Interrupt Set-pending Registers
The NVIC_ISPR0-NVIC_ISPR7 registers force interrupts into the pending state, and show
which interrupts are pending. See the register summary in Table 4-2 on page 4-3 for the register
attributes.
The bit assignments are:
Note
Writing 1 to the ISPR bit corresponding to:
• an interrupt that is pending has no effect
• a disabled interrupt sets the state of that interrupt to pending.
Table 4-5 ICER bit assignments
Bits Name Function
[31:0] CLRENA Interrupt clear-enable bits.
Write:
0 = no effect
1 = disable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
CLRENA bits
31 0
Table 4-6 ISPR bit assignments
Bits Name Function
[31:0] SETPEND Interrupt set-pending bits.
Write:
0 = no effect
1 = changes interrupt state to pending.
Read:
0 = interrupt is not pending
1 = interrupt is pending.
SETPEND bits
31 0